diff --git a/include/arm_defs.hpp b/include/arm_defs.hpp
index 03143932..ef017775 100644
--- a/include/arm_defs.hpp
+++ b/include/arm_defs.hpp
@@ -61,6 +61,7 @@ namespace FPSCR {
         RoundToZero = 3 << 22,
 
         // Default FPSCR value for threads
-        ThreadDefault = DefaultNan | FlushToZero | RoundToZero | IXC
+        ThreadDefault = DefaultNan | FlushToZero | RoundToZero,
+        MainThreadDefault = ThreadDefault | IXC;
     };
 }
\ No newline at end of file
diff --git a/src/core/CPU/cpu_dynarmic.cpp b/src/core/CPU/cpu_dynarmic.cpp
index 9092b7a3..94903c2f 100644
--- a/src/core/CPU/cpu_dynarmic.cpp
+++ b/src/core/CPU/cpu_dynarmic.cpp
@@ -9,7 +9,7 @@ CPU::CPU(Memory& mem, Kernel& kernel) : mem(mem), env(mem, kernel, *this) {
     config.arch_version = Dynarmic::A32::ArchVersion::v6K;
     config.callbacks = &env;
     config.coprocessors[15] = cp15;
-    // config.define_unpredictable_behaviour = true;
+    config.define_unpredictable_behaviour = true;
     config.global_monitor = &exclusiveMonitor;
     config.processor_id = 0;
     
@@ -18,7 +18,7 @@ CPU::CPU(Memory& mem, Kernel& kernel) : mem(mem), env(mem, kernel, *this) {
 
 void CPU::reset() {
     setCPSR(CPSR::UserMode);
-    setFPSCR(FPSCR::ThreadDefault);
+    setFPSCR(FPSCR::MainThreadDefault);
     env.totalTicks = 0;
 
     cp15->reset();
diff --git a/src/core/PICA/regs.cpp b/src/core/PICA/regs.cpp
index 7a2c15c4..10ae9b46 100644
--- a/src/core/PICA/regs.cpp
+++ b/src/core/PICA/regs.cpp
@@ -4,8 +4,13 @@
 using namespace Floats;
 
 u32 GPU::readReg(u32 address) {
-	log("Ignoring read from GPU register %08X\n", address);
-	return 0;
+	if (address >= 0x1EF01000 && address < 0x1EF01C00) { // Internal registers
+		const u32 index = (address - 0x1EF01000) / sizeof(u32);
+		return readInternalReg(index);
+	} else {
+		log("Ignoring read to external GPU register %08X.\n", address);
+		return 0;
+	}
 }
 
 void GPU::writeReg(u32 address, u32 value) {