[CPU] Move ARM definitions to arm_defs.hpp file

CMakeLists.txt

@@ -59,7 +59,7 @@ set(HEADER_FILES include/emulator.hpp include/helpers.hpp include/opengl.hpp inc
                  include/dynarmic_cp15.hpp include/kernel/resource_limits.hpp include/kernel/kernel_types.hpp
                  include/kernel/config_mem.hpp include/services/service_manager.hpp include/services/apt.hpp
                  include/kernel/handles.hpp include/services/hid.hpp include/services/fs.hpp
-                 include/services/gsp_gpu.hpp include/services/gsp_lcd.hpp
+                 include/services/gsp_gpu.hpp include/services/gsp_lcd.hpp include/arm_defs.hpp
 )
 
 set(THIRD_PARTY_SOURCE_FILES third_party/imgui/imgui.cpp

include/arm_defs.hpp

@@ -0,0 +1,58 @@
+#pragma once
+
+// Status register definitions
+namespace CPSR {
+    enum : u32 {
+        // Privilege modes
+        UserMode = 16,
+        FIQMode = 17,
+        IRQMode = 18,
+        SVCMode = 19,
+        AbortMode = 23,
+        UndefMode = 27,
+        SystemMode = 31,
+
+        // If (CPSR & Thumb) the we're in thumb mode
+        Thumb = 1 << 5
+	};
+}
+
+namespace FPSCR {
+    // FPSCR Flags
+    enum : u32 {
+        NFlag = (1U << 31U), // Negative condition flag
+        ZFlag = (1 << 30),   // Zero condition flag
+        CFlag = (1 << 29),   // Carry condition flag
+        VFlag = (1 << 28),   // Overflow condition flag
+
+        QC = (1 << 27),   // Cumulative saturation bit
+        AHP = (1 << 26),   // Alternative half-precision control bit
+        DefaultNan = (1 << 25),   // Default NaN mode control bit
+        FlushToZero = (1 << 24),   // Flush abnormals to 0 control bit
+        RmodeMask = (3 << 22),   // Rounding Mode bit mask
+        StrideMask = (3 << 20),   // Vector stride bit mask
+        LengthMask = (7 << 16),   // Vector length bit mask
+
+        IDE = (1 << 15), // Input Denormal exception trap enable.
+        IXE = (1 << 12), // Inexact exception trap enable
+        UFE = (1 << 11), // Undeflow exception trap enable
+        OFE = (1 << 10), // Overflow exception trap enable
+        DZE = (1 << 9),  // Division by Zero exception trap enable
+        IOE = (1 << 8),  // Invalid Operation exception trap enable
+
+        IDC = (1 << 7), // Input Denormal cumulative exception bit
+        IXC = (1 << 4), // Inexact cumulative exception bit
+        UFC = (1 << 3), // Undeflow cumulative exception bit
+        OFC = (1 << 2), // Overflow cumulative exception bit
+        DZC = (1 << 1), // Division by Zero cumulative exception bit
+        IOC = (1 << 0), // Invalid Operation cumulative exception bit
+
+        RoundNearest = (0 << 22),
+        RoundPlusInf = (1 << 22),
+        RoundMinusInf = (2 << 22),
+        RoundToZero = (3 << 22),
+
+        // Default FPSCR value for threads
+        ThreadDefault = DefaultNan | FlushToZero | RoundToZero | IXC
+    };
+}

include/cpu.hpp

@@ -6,61 +6,4 @@
 #error KVM CPU is not implemented yet
 #else
 #error No CPU core implemented :(
-#endif
+#endif
-
-// Status register definitions
-namespace CPSR {
-    enum : u32 {
-        // Privilege modes
-        UserMode = 16,
-        FIQMode = 17,
-        IRQMode = 18,
-        SVCMode = 19,
-        AbortMode = 23,
-        UndefMode = 27,
-        SystemMode = 31,
-
-        // If (CPSR & Thumb) the we're in thumb mode
-        Thumb = 1 << 5
-	};
-}
-
-namespace FPSCR {
-    // FPSCR Flags
-    enum : u32 {
-        NFlag = (1U << 31U), // Negative condition flag
-        ZFlag = (1 << 30),   // Zero condition flag
-        CFlag = (1 << 29),   // Carry condition flag
-        VFlag = (1 << 28),   // Overflow condition flag
-
-        QC = (1 << 27),   // Cumulative saturation bit
-        AHP = (1 << 26),   // Alternative half-precision control bit
-        DefaultNan = (1 << 25),   // Default NaN mode control bit
-        FlushToZero = (1 << 24),   // Flush abnormals to 0 control bit
-        RmodeMask = (3 << 22),   // Rounding Mode bit mask
-        StrideMask = (3 << 20),   // Vector stride bit mask
-        LengthMask = (7 << 16),   // Vector length bit mask
-
-        IDE = (1 << 15), // Input Denormal exception trap enable.
-        IXE = (1 << 12), // Inexact exception trap enable
-        UFE = (1 << 11), // Undeflow exception trap enable
-        OFE = (1 << 10), // Overflow exception trap enable
-        DZE = (1 << 9),  // Division by Zero exception trap enable
-        IOE = (1 << 8),  // Invalid Operation exception trap enable
-
-        IDC = (1 << 7), // Input Denormal cumulative exception bit
-        IXC = (1 << 4), // Inexact cumulative exception bit
-        UFC = (1 << 3), // Undeflow cumulative exception bit
-        OFC = (1 << 2), // Overflow cumulative exception bit
-        DZC = (1 << 1), // Division by Zero cumulative exception bit
-        IOC = (1 << 0), // Invalid Operation cumulative exception bit
-
-        RoundNearest = (0 << 22),
-        RoundPlusInf = (1 << 22),
-        RoundMinusInf = (2 << 22),
-        RoundToZero = (3 << 22),
-
-        // Default FPSCR value for threads
-        ThreadDefault = DefaultNan | FlushToZero | RoundToZero | IXC
-    };
-}

src/core/CPU/cpu_dynarmic.cpp

@@ -1,5 +1,6 @@
 #ifdef CPU_DYNARMIC
 #include "cpu_dynarmic.hpp"
+#include "arm_defs.hpp"
 
 CPU::CPU(Memory& mem, Kernel& kernel) : mem(mem), env(mem, kernel, *this) {
     cp15 = std::make_shared<CP15>();
@@ -16,8 +17,8 @@ CPU::CPU(Memory& mem, Kernel& kernel) : mem(mem), env(mem, kernel, *this) {
 }
 
 void CPU::reset() {
-    // ARM mode, all flags disabled, interrupts and aborts all enabled, user mode
+    setCPSR(CPSR::UserMode);
-    setCPSR(0x00000010);
+    setFPSCR(FPSCR::ThreadDefault);
 
     cp15->reset();
     cp15->setTLSBase(VirtualAddrs::TLSBase); // Set cp15 TLS pointer to the main thread's thread-local storage

src/core/kernel/threads.cpp

@@ -1,5 +1,6 @@
 #include <cstring>
 #include "kernel.hpp"
+#include "arm_defs.hpp"
 // This header needs to be included because I did stupid forward decl hack so the kernel and CPU can both access each other
 #include "cpu.hpp"
 #include "resource_limits.hpp"