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[GPU] Stub FlushCacheRange, increase size of shader memory
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4930c1a947
commit
5f7804e99f
3 changed files with 15 additions and 8 deletions
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@ -148,8 +148,8 @@ class PICAShader {
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bool isCondTrue(u32 instruction);
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bool isCondTrue(u32 instruction);
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public:
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public:
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std::array<u32, 512> loadedShader; // Currently loaded & active shader
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std::array<u32, 4096> loadedShader; // Currently loaded & active shader
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std::array<u32, 512> bufferedShader; // Shader to be transferred when the SH_CODETRANSFER_END reg gets written to
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std::array<u32, 4096> bufferedShader; // Shader to be transferred when the SH_CODETRANSFER_END reg gets written to
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u32 entrypoint = 0; // Initial shader PC
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u32 entrypoint = 0; // Initial shader PC
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u32 boolUniform;
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u32 boolUniform;
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@ -164,12 +164,12 @@ public:
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// Theese functions are in the header to be inlined more easily, though with LTO I hope I'll be able to move them
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// Theese functions are in the header to be inlined more easily, though with LTO I hope I'll be able to move them
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void finalize() {
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void finalize() {
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std::memcpy(&loadedShader[0], &bufferedShader[0], 512 * sizeof(u32));
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std::memcpy(&loadedShader[0], &bufferedShader[0], 4096 * sizeof(u32));
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}
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}
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void setBufferIndex(u32 index) {
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void setBufferIndex(u32 index) {
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if (index != 0) Helpers::panic("Is this register 9 or 11 bit?");
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if (index != 0) Helpers::panic("How many bits is the shader buffer index reg meant to be?");
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bufferIndex = (index >> 2) & 0x1ff;
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bufferIndex = (index >> 2) & 0xfff;
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}
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}
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void setOpDescriptorIndex(u32 index) {
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void setOpDescriptorIndex(u32 index) {
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@ -177,9 +177,9 @@ public:
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}
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}
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void uploadWord(u32 word) {
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void uploadWord(u32 word) {
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if (bufferIndex >= 511) Helpers::panic("o no");
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if (bufferIndex >= 4095) Helpers::panic("o no, shader upload overflew");
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bufferedShader[bufferIndex++] = word;
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bufferedShader[bufferIndex++] = word;
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bufferIndex &= 0x1ff;
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bufferIndex &= 0xfff;
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}
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}
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void uploadDescriptor(u32 word) {
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void uploadDescriptor(u32 word) {
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@ -43,6 +43,7 @@ class GPUService {
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void processCommandList(u32* cmd);
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void processCommandList(u32* cmd);
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void memoryFill(u32* cmd);
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void memoryFill(u32* cmd);
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void triggerDisplayTransfer(u32* cmd);
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void triggerDisplayTransfer(u32* cmd);
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void flushCacheRegions(u32* cmd);
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public:
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public:
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GPUService(Memory& mem, GPU& gpu, u32& currentPID) : mem(mem), gpu(gpu), currentPID(currentPID) {}
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GPUService(Memory& mem, GPU& gpu, u32& currentPID) : mem(mem), gpu(gpu), currentPID(currentPID) {}
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@ -18,7 +18,8 @@ namespace GXCommands {
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enum : u32 {
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enum : u32 {
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ProcessCommandList = 1,
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ProcessCommandList = 1,
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MemoryFill = 2,
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MemoryFill = 2,
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TriggerDisplayTransfer = 3
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TriggerDisplayTransfer = 3,
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FlushCacheRegions = 5
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};
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};
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}
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}
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@ -214,6 +215,7 @@ void GPUService::processCommandBuffer() {
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case GXCommands::ProcessCommandList: processCommandList(cmd); break;
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case GXCommands::ProcessCommandList: processCommandList(cmd); break;
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case GXCommands::MemoryFill: memoryFill(cmd); break;
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case GXCommands::MemoryFill: memoryFill(cmd); break;
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case GXCommands::TriggerDisplayTransfer: triggerDisplayTransfer(cmd); break;
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case GXCommands::TriggerDisplayTransfer: triggerDisplayTransfer(cmd); break;
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case GXCommands::FlushCacheRegions: flushCacheRegions(cmd); break;
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default: Helpers::panic("GSP::GPU::ProcessCommands: Unknown cmd ID %d", cmdID);
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default: Helpers::panic("GSP::GPU::ProcessCommands: Unknown cmd ID %d", cmdID);
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}
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}
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@ -252,6 +254,10 @@ void GPUService::triggerDisplayTransfer(u32* cmd) {
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requestInterrupt(GPUInterrupt::PPF); // Send "Display transfer finished" interrupt
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requestInterrupt(GPUInterrupt::PPF); // Send "Display transfer finished" interrupt
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}
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}
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void GPUService::flushCacheRegions(u32* cmd) {
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log("GSP::GPU::FlushCacheRegions (Stubbed)\n");
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}
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// Actually send command list (aka display list) to GPU
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// Actually send command list (aka display list) to GPU
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void GPUService::processCommandList(u32* cmd) {
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void GPUService::processCommandList(u32* cmd) {
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u32 address = cmd[1] & ~7; // Buffer address
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u32 address = cmd[1] & ~7; // Buffer address
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