From 71fd8de92fc7193a7a2fbde1a600822cdbcc3aee Mon Sep 17 00:00:00 2001 From: wheremyfoodat Date: Sun, 11 Jun 2023 22:08:02 +0300 Subject: [PATCH] [Shader JIT] Add MIN --- src/core/PICA/dynapica/shader_rec_emitter_x64.cpp | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/core/PICA/dynapica/shader_rec_emitter_x64.cpp b/src/core/PICA/dynapica/shader_rec_emitter_x64.cpp index 8317662e..9b9a3b04 100644 --- a/src/core/PICA/dynapica/shader_rec_emitter_x64.cpp +++ b/src/core/PICA/dynapica/shader_rec_emitter_x64.cpp @@ -117,6 +117,7 @@ void ShaderEmitter::compileInstruction(const PICAShader& shaderUnit) { case ShaderOpcodes::MOV: recMOV(shaderUnit, instruction); break; case ShaderOpcodes::MOVA: recMOVA(shaderUnit, instruction); break; case ShaderOpcodes::MAX: recMAX(shaderUnit, instruction); break; + case ShaderOpcodes::MIN: recMIN(shaderUnit, instruction); break; case ShaderOpcodes::MUL: recMUL(shaderUnit, instruction); break; case ShaderOpcodes::NOP: break; case ShaderOpcodes::RCP: recRCP(shaderUnit, instruction); break; @@ -445,6 +446,19 @@ void ShaderEmitter::recMAX(const PICAShader& shader, u32 instruction) { storeRegister(src1_xmm, shader, dest, operandDescriptor); } +void ShaderEmitter::recMIN(const PICAShader& shader, u32 instruction) { + const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f]; + const u32 src1 = getBits<12, 7>(instruction); + const u32 src2 = getBits<7, 5>(instruction); // src2 coming first because PICA moment + const u32 idx = getBits<19, 2>(instruction); + const u32 dest = getBits<21, 5>(instruction); + + loadRegister<1>(src1_xmm, shader, src1, idx, operandDescriptor); + loadRegister<2>(src2_xmm, shader, src2, 0, operandDescriptor); + minps(src1_xmm, src2_xmm); + storeRegister(src1_xmm, shader, dest, operandDescriptor); +} + void ShaderEmitter::recMUL(const PICAShader& shader, u32 instruction) { const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f]; const u32 src1 = getBits<12, 7>(instruction);