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[PICA interpreter] Implement dp4, end
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3 changed files with 49 additions and 9 deletions
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@ -12,7 +12,9 @@ enum class ShaderType {
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namespace ShaderOpcodes {
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namespace ShaderOpcodes {
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enum : u32 {
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enum : u32 {
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MOV = 0x13
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DP4 = 0x02,
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MOV = 0x13,
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END = 0x22
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};
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};
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}
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}
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@ -31,11 +33,13 @@ class PICAShader {
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std::array<vec4f, 16> tempRegisters;
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std::array<vec4f, 16> tempRegisters;
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ShaderType type;
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ShaderType type;
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// Shader opcodes
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void mov(u32 instruction);
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vec4f getSource(u32 source);
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vec4f getSource(u32 source);
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vec4f& getDest(u32 dest);
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vec4f& getDest(u32 dest);
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// Shader opcodes
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void dp4(u32 instruction);
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void mov(u32 instruction);
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// src1, src2 and src3 have different negation & component swizzle bits in the operand descriptor
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// src1, src2 and src3 have different negation & component swizzle bits in the operand descriptor
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// https://problemkaputt.github.io/gbatek.htm#3dsgpushaderinstructionsetopcodesummary in the
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// https://problemkaputt.github.io/gbatek.htm#3dsgpushaderinstructionsetopcodesummary in the
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// "Shader Operand Descriptors" section
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// "Shader Operand Descriptors" section
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@ -75,6 +79,14 @@ class PICAShader {
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return ret;
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return ret;
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}
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}
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template <int sourceIndex>
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vec4f getSourceSwizzled(u32 source, u32 opDescriptor) {
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vec4f srcVector = getSource(source);
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srcVector = swizzle<sourceIndex>(srcVector, opDescriptor);
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return srcVector;
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}
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public:
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public:
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std::array<u32, 512> loadedShader; // Currently loaded & active shader
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std::array<u32, 512> loadedShader; // Currently loaded & active shader
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std::array<u32, 512> bufferedShader; // Shader to be transferred when the SH_CODETRANSFER_END reg gets written to
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std::array<u32, 512> bufferedShader; // Shader to be transferred when the SH_CODETRANSFER_END reg gets written to
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@ -8,6 +8,8 @@ void PICAShader::run() {
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const u32 opcode = instruction >> 26; // Top 6 bits are the opcode
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const u32 opcode = instruction >> 26; // Top 6 bits are the opcode
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switch (opcode) {
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switch (opcode) {
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case ShaderOpcodes::DP4: dp4(instruction); break;
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case ShaderOpcodes::END: return; // Stop running shader
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case ShaderOpcodes::MOV: mov(instruction); break;
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case ShaderOpcodes::MOV: mov(instruction); break;
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default:Helpers::panic("Unimplemented PICA instruction %08X (Opcode = %02X)", instruction, opcode);
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default:Helpers::panic("Unimplemented PICA instruction %08X (Opcode = %02X)", instruction, opcode);
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}
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}
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@ -15,16 +17,20 @@ void PICAShader::run() {
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}
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}
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PICAShader::vec4f PICAShader::getSource(u32 source) {
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PICAShader::vec4f PICAShader::getSource(u32 source) {
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if (source < 16)
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if (source < 0x10)
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return attributes[source];
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return attributes[source];
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else if (source >= 0x20 && source <= 0x7f)
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else if (source < 0x20)
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return tempRegisters[source - 0x10];
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else if (source <= 0x7f)
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return floatUniforms[source - 0x20];
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return floatUniforms[source - 0x20];
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Helpers::panic("[PICA] Unimplemented source value: %X", source);
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Helpers::panic("[PICA] Unimplemented source value: %X", source);
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}
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}
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PICAShader::vec4f& PICAShader::getDest(u32 dest) {
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PICAShader::vec4f& PICAShader::getDest(u32 dest) {
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if (dest >= 0x10 && dest <= 0x1f) { // Temporary registers
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if (dest <= 0x6) {
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return outputs[dest];
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} else if (dest >= 0x10 && dest <= 0x1f) { // Temporary registers
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return tempRegisters[dest - 0x10];
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return tempRegisters[dest - 0x10];
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}
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}
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Helpers::panic("[PICA] Unimplemented dest: %X", dest);
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Helpers::panic("[PICA] Unimplemented dest: %X", dest);
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@ -37,8 +43,7 @@ void PICAShader::mov(u32 instruction) {
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const u32 dest = (instruction >> 21) & 0x1f;
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const u32 dest = (instruction >> 21) & 0x1f;
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if (idx) Helpers::panic("[PICA] MOV: idx != 0");
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if (idx) Helpers::panic("[PICA] MOV: idx != 0");
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vec4f srcVector = getSource(src);
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vec4f srcVector = getSourceSwizzled<1>(src, operandDescriptor);
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srcVector = swizzle<1>(srcVector, operandDescriptor);
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vec4f& destVector = getDest(dest);
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vec4f& destVector = getDest(dest);
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// Destination component mask. Tells us which lanes of the destination register will be written to
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// Destination component mask. Tells us which lanes of the destination register will be written to
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@ -49,3 +54,26 @@ void PICAShader::mov(u32 instruction) {
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}
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}
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}
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}
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}
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}
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void PICAShader::dp4(u32 instruction) {
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const u32 operandDescriptor = operandDescriptors[instruction & 0x7f];
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const u32 src1 = (instruction >> 12) & 0x7f;
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const u32 src2 = (instruction >> 7) & 0x1f; // src2 coming first because PICA moment
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const u32 idx = (instruction >> 19) & 3;
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const u32 dest = (instruction >> 21) & 0x1f;
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if (idx) Helpers::panic("[PICA] DP4: idx != 0");
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vec4f srcVec1 = getSourceSwizzled<1>(src1, operandDescriptor);
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vec4f srcVec2 = getSourceSwizzled<2>(src2, operandDescriptor);
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vec4f& destVector = getDest(dest);
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f24 dot = srcVec1[0] * srcVec2[0] + srcVec1[1] * srcVec2[1] + srcVec1[2] * srcVec2[2] + srcVec1[3] * srcVec2[3];
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// Destination component mask. Tells us which lanes of the destination register will be written to
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u32 componentMask = operandDescriptor & 0xf;
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for (int i = 0; i < 4; i++) {
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if (componentMask & (1 << i)) {
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destVector[3 - i] = dot;
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}
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}
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}
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@ -18,7 +18,7 @@ void PICAShader::reset() {
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opDescriptorIndex = 0;
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opDescriptorIndex = 0;
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f32UniformTransfer = false;
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f32UniformTransfer = false;
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const vec4f zero = vec4f({ f24::fromFloat32(0.0), f24::fromFloat32(0.0), f24::fromFloat32(0.0), f24::fromFloat32(0.0) });
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const vec4f zero = vec4f({ f24::zero(), f24::zero(), f24::zero(), f24::zero() });
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attributes.fill(zero);
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attributes.fill(zero);
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floatUniforms.fill(zero);
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floatUniforms.fill(zero);
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outputs.fill(zero);
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outputs.fill(zero);
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