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[Shader JIT] Compile MAD to FMA when possible

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wheremyfoodat 2023-06-30 02:02:56 +03:00
parent cd04ed3770
commit 8a13b8c878
2 changed files with 20 additions and 9 deletions
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2
include/PICA/dynapica/shader_rec_emitter_x64.hpp
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@ -36,6 +36,7 @@ class ShaderEmitter : public Xbyak::CodeGenerator {
bool haveSSE4_1 = false; // Shows if the CPU supports SSE4.1
bool haveAVX = false; // Shows if the CPU supports AVX (NOT AVX2, NOT AVX512. Regular AVX)
bool haveFMA3 = false; // Shows if the CPU supports FMA3
// Compile all instructions from [current recompiler PC, end)
void compileUntil(const PICAShader& shaderUnit, u32 endPC);
@ -112,6 +113,7 @@ public:
haveSSE4_1 = cpu.has(Xbyak::util::Cpu::tSSE41);
haveAVX = cpu.has(Xbyak::util::Cpu::tAVX);
haveFMA3 = cpu.has(Xbyak::util::Cpu::tFMA);
if (!cpu.has(Xbyak::util::Cpu::tSSE3)) {
Helpers::panic("This CPU does not support SSE3. Please use the shader interpreter instead");

9
src/core/PICA/dynapica/shader_rec_emitter_x64.cpp
View file

@ -580,6 +580,14 @@ void ShaderEmitter::recMAD(const PICAShader& shader, u32 instruction) {
loadRegister<3>(src3_xmm, shader, src3, 0, operandDescriptor);
// TODO: Implement safe PICA mul
// If we have FMA3, optimize MAD to use FMA
if (haveFMA3) {
vfmadd213ps(src1_xmm, src2_xmm, src3_xmm);
storeRegister(src1_xmm, shader, dest, operandDescriptor);
}
// If we don't have FMA3, do a multiplication and addition
else {
// Multiply src1 * src2
if (haveAVX) {
vmulps(scratch1, src1_xmm, src2_xmm);
@ -592,6 +600,7 @@ void ShaderEmitter::recMAD(const PICAShader& shader, u32 instruction) {
addps(scratch1, src3_xmm);
storeRegister(scratch1, shader, dest, operandDescriptor);
}
}
void ShaderEmitter::recCMP(const PICAShader& shader, u32 instruction) {
const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];