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[CPU] Clean up ARM defs

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wheremyfoodat 2022-09-20 15:51:05 +03:00
parent 33fc380896
commit 919951516a
1 changed files with 37 additions and 29 deletions
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66
include/arm_defs.hpp
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@ -12,45 +12,53 @@ namespace CPSR {
UndefMode = 27, UndefMode = 27,
SystemMode = 31, SystemMode = 31,
// If (CPSR & Thumb) the we're in thumb mode // CPSR flag fields
Thumb = 1 << 5 Thumb = 1 << 5,
FIQDisable = 1 << 6,
IRQDisable = 1 << 7,
StickyOverflow = 1 << 27,
Overflow = 1 << 28,
Carry = 1 << 29,
Zero = 1 << 30,
Sign = 1U << 31U
}; };
} }
namespace FPSCR { namespace FPSCR {
// FPSCR Flags // FPSCR Flags
enum : u32 { enum : u32 {
NFlag = (1U << 31U), // Negative condition flag Sign = 1U << 31U, // Negative condition flag
ZFlag = (1 << 30), // Zero condition flag Zero = 1 << 30, // Zero condition flag
CFlag = (1 << 29), // Carry condition flag Carry = 1 << 29, // Carry condition flag
VFlag = (1 << 28), // Overflow condition flag Overflow = 1 << 28, // Overflow condition flag
QC = (1 << 27), // Cumulative saturation bit QC = 1 << 27, // Cumulative saturation bit
AHP = (1 << 26), // Alternative half-precision control bit AHP = 1 << 26, // Alternative half-precision control bit
DefaultNan = (1 << 25), // Default NaN mode control bit DefaultNan = 1 << 25, // Default NaN mode control bit
FlushToZero = (1 << 24), // Flush abnormals to 0 control bit FlushToZero = 1 << 24, // Flush abnormals to 0 control bit
RmodeMask = (3 << 22), // Rounding Mode bit mask RmodeMask = 3 << 22, // Rounding Mode bit mask
StrideMask = (3 << 20), // Vector stride bit mask StrideMask = 3 << 20, // Vector stride bit mask
LengthMask = (7 << 16), // Vector length bit mask LengthMask = 7 << 16, // Vector length bit mask
IDE = (1 << 15), // Input Denormal exception trap enable. IDE = 1 << 15, // Input Denormal exception trap enable.
IXE = (1 << 12), // Inexact exception trap enable IXE = 1 << 12, // Inexact exception trap enable
UFE = (1 << 11), // Undeflow exception trap enable UFE = 1 << 11, // Undeflow exception trap enable
OFE = (1 << 10), // Overflow exception trap enable OFE = 1 << 10, // Overflow exception trap enable
DZE = (1 << 9), // Division by Zero exception trap enable DZE = 1 << 9, // Division by Zero exception trap enable
IOE = (1 << 8), // Invalid Operation exception trap enable IOE = 1 << 8, // Invalid Operation exception trap enable
IDC = (1 << 7), // Input Denormal cumulative exception bit IDC = 1 << 7, // Input Denormal cumulative exception bit
IXC = (1 << 4), // Inexact cumulative exception bit IXC = 1 << 4, // Inexact cumulative exception bit
UFC = (1 << 3), // Undeflow cumulative exception bit UFC = 1 << 3, // Undeflow cumulative exception bit
OFC = (1 << 2), // Overflow cumulative exception bit OFC = 1 << 2, // Overflow cumulative exception bit
DZC = (1 << 1), // Division by Zero cumulative exception bit DZC = 1 << 1, // Division by Zero cumulative exception bit
IOC = (1 << 0), // Invalid Operation cumulative exception bit IOC = 1 << 0, // Invalid Operation cumulative exception bit
RoundNearest = (0 << 22), // VFP rounding modes
RoundPlusInf = (1 << 22), RoundNearest = 0 << 22,
RoundMinusInf = (2 << 22), RoundPlusInf = 1 << 22,
RoundToZero = (3 << 22), RoundMinusInf = 2 << 22,
RoundToZero = 3 << 22,
// Default FPSCR value for threads // Default FPSCR value for threads
ThreadDefault = DefaultNan | FlushToZero | RoundToZero | IXC ThreadDefault = DefaultNan | FlushToZero | RoundToZero | IXC