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We can now change threads
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10 changed files with 159 additions and 14 deletions
include
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@ -6,4 +6,61 @@
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#error KVM CPU is not implemented yet
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#else
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#error No CPU core implemented :(
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#endif
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#endif
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// Status register definitions
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namespace CPSR {
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enum : u32 {
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// Privilege modes
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UserMode = 16,
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FIQMode = 17,
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IRQMode = 18,
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SVCMode = 19,
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AbortMode = 23,
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UndefMode = 27,
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SystemMode = 31,
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// If (CPSR & Thumb) the we're in thumb mode
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Thumb = 1 << 5
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};
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}
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namespace FPSCR {
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// FPSCR Flags
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enum : u32 {
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NFlag = (1U << 31U), // Negative condition flag
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ZFlag = (1 << 30), // Zero condition flag
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CFlag = (1 << 29), // Carry condition flag
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VFlag = (1 << 28), // Overflow condition flag
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QC = (1 << 27), // Cumulative saturation bit
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AHP = (1 << 26), // Alternative half-precision control bit
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DefaultNan = (1 << 25), // Default NaN mode control bit
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FlushToZero = (1 << 24), // Flush abnormals to 0 control bit
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RmodeMask = (3 << 22), // Rounding Mode bit mask
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StrideMask = (3 << 20), // Vector stride bit mask
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LengthMask = (7 << 16), // Vector length bit mask
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IDE = (1 << 15), // Input Denormal exception trap enable.
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IXE = (1 << 12), // Inexact exception trap enable
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UFE = (1 << 11), // Undeflow exception trap enable
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OFE = (1 << 10), // Overflow exception trap enable
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DZE = (1 << 9), // Division by Zero exception trap enable
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IOE = (1 << 8), // Invalid Operation exception trap enable
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IDC = (1 << 7), // Input Denormal cumulative exception bit
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IXC = (1 << 4), // Inexact cumulative exception bit
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UFC = (1 << 3), // Undeflow cumulative exception bit
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OFC = (1 << 2), // Overflow cumulative exception bit
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DZC = (1 << 1), // Division by Zero cumulative exception bit
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IOC = (1 << 0), // Invalid Operation cumulative exception bit
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RoundNearest = (0 << 22),
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RoundPlusInf = (1 << 22),
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RoundMinusInf = (2 << 22),
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RoundToZero = (3 << 22),
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// Default FPSCR value for threads
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ThreadDefault = DefaultNan | FlushToZero | RoundToZero | IXC
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};
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}
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