[PICA] Implement RCP

This commit is contained in:
wheremyfoodat 2023-01-07 01:34:34 +02:00
parent 64de1391ab
commit bbb62a83d0
2 changed files with 23 additions and 0 deletions

View file

@ -18,6 +18,7 @@ namespace ShaderOpcodes {
MUL = 0x08,
MAX = 0x0C,
MIN = 0x0D,
RCP = 0x0E,
RSQ = 0x0F,
MOVA = 0x12,
MOV = 0x13,
@ -99,6 +100,7 @@ class PICAShader {
void mov(u32 instruction);
void mova(u32 instruction);
void mul(u32 instruction);
void rcp(u32 instruction);
void rsq(u32 instruction);
// src1, src2 and src3 have different negation & component swizzle bits in the operand descriptor

View file

@ -30,6 +30,7 @@ void PICAShader::run() {
case ShaderOpcodes::MOVA: mova(instruction); break;
case ShaderOpcodes::MUL: mul(instruction); break;
case ShaderOpcodes::NOP: break; // Do nothing
case ShaderOpcodes::RCP: rcp(instruction); break;
case ShaderOpcodes::RSQ: rsq(instruction); break;
case 0x38: case 0x39: case 0x3A: case 0x3B: case 0x3C: case 0x3D: case 0x3E: case 0x3F:
@ -292,6 +293,26 @@ void PICAShader::dp4(u32 instruction) {
}
}
void PICAShader::rcp(u32 instruction) {
const u32 operandDescriptor = operandDescriptors[instruction & 0x7f];
const u32 src1 = (instruction >> 12) & 0x7f;
const u32 idx = (instruction >> 19) & 3;
const u32 dest = (instruction >> 21) & 0x1f;
if (idx) Helpers::panic("[PICA] RCP: idx != 0");
vec4f srcVec1 = getSourceSwizzled<1>(src1, operandDescriptor);
vec4f& destVector = getDest(dest);
f24 res = f24::fromFloat32(1.0f) / srcVec1[0];
u32 componentMask = operandDescriptor & 0xf;
for (int i = 0; i < 4; i++) {
if (componentMask & (1 << i)) {
destVector[3 - i] = res;
}
}
}
void PICAShader::rsq(u32 instruction) {
const u32 operandDescriptor = operandDescriptors[instruction & 0x7f];
const u32 src1 = (instruction >> 12) & 0x7f;