mirror of
https://github.com/wheremyfoodat/Panda3DS.git
synced 2025-04-07 14:45:41 +12:00
KVM support
Co-authored-by: wheremyfoodat <44909372+wheremyfoodat@users.noreply.github.com> Co-authored-by: hazelwiss <hazelwiss.rs@gmail.com>
This commit is contained in:
offtkp
parent
91f8f81418
commit
bbbc7fb1f2
6 changed files with 517 additions and 4 deletions
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@ -43,6 +43,7 @@ option(ENABLE_HTTP_SERVER "Enable HTTP server. Used for Discord bot support" OFF
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option(ENABLE_DISCORD_RPC "Compile with Discord RPC support (disabled by default)" ON)
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option(ENABLE_LUAJIT "Enable scripting with the Lua programming language" ON)
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option(ENABLE_QT_GUI "Enable the Qt GUI. If not selected then the emulator uses a minimal SDL-based UI instead" OFF)
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option(USE_KVM "Use KVM instead of Dynarmic" OFF)
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option(BUILD_HYDRA_CORE "Build a Hydra core" OFF)
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option(BUILD_LIBRETRO_CORE "Build a Libretro core" OFF)
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@ -155,12 +156,14 @@ else()
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set(HOST_ARM64 FALSE)
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endif()
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if(HOST_X64 OR HOST_ARM64)
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if(NOT USE_KVM AND (HOST_X64 OR HOST_ARM64))
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set(DYNARMIC_TESTS OFF)
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#set(DYNARMIC_NO_BUNDLED_FMT ON)
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set(DYNARMIC_FRONTENDS "A32" CACHE STRING "")
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add_subdirectory(third_party/dynarmic)
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add_compile_definitions(CPU_DYNARMIC)
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elseif(USE_KVM AND HOST_ARM64)
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add_compile_definitions(CPU_KVM)
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else()
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message(FATAL_ERROR "Currently unsupported CPU architecture")
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endif()
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@ -3,7 +3,7 @@
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#ifdef CPU_DYNARMIC
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#include "cpu_dynarmic.hpp"
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#elif defined(CPU_KVM)
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#error KVM CPU is not implemented yet
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#include "cpu_kvm.hpp"
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#else
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#error No CPU core implemented :(
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#endif
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235
include/cpu_kvm.hpp
Normal file
235
include/cpu_kvm.hpp
Normal file
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@ -0,0 +1,235 @@
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#pragma once
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#include <fcntl.h>
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#include <linux/kvm.h>
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#include <sys/ioctl.h>
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#include <sys/types.h>
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#include <sys/mman.h>
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#include "helpers.hpp"
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#include "kernel.hpp"
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#include "memory.hpp"
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#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
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struct MmuTables {
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u32 level1[4096];
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u32 level2SectionTables[256];
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};
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constexpr u32 hypervisorCodeAddress = 0xD0000000;
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constexpr u32 hypervisorDataAddress = 0xE0000000;
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constexpr u32 hypervisorCodeSize = hypervisorDataAddress - hypervisorCodeAddress;
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constexpr u32 hypervisorDataSize = hypervisorCodeSize;
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constexpr u32 mmuTableOffset = hypervisorDataSize - sizeof(MmuTables);
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constexpr u32 mmuTableAddress = hypervisorDataAddress + mmuTableOffset;
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constexpr u32 exitCodeOffset = 0; // at start of hypervisor data segment
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constexpr u32 customEntryOffset = 0x100000; // arbitrary, far enough that the exit code won't ever overlap with this
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constexpr u32 guestStateOffset = 0x200000; // also arbitrary, store the guest state here upon exit
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struct GuestState
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{
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std::array<u32, 16> regs;
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std::array<u32, 32> fprs;
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u32 cpsr;
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u32 fpscr;
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// u32 tlsBase?
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// u64 ticks?
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};
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struct Environment {
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Environment(Memory& mem, Kernel& kernel) : mem(mem), kernel(kernel) {
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u32 currentMemorySlot = 0;
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kvmDescriptor = open("/dev/kvm", O_RDWR);
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if (kvmDescriptor < 0) {
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Helpers::panic("Failed to open /dev/kvm");
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}
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vmDescriptor = ioctl(kvmDescriptor, KVM_CREATE_VM, 0);
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if (vmDescriptor < 0) {
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Helpers::panic("Failed to create KVM VM");
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}
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if (ioctl(vmDescriptor, KVM_CHECK_EXTENSION, KVM_CAP_ARM_EL1_32BIT) <= 0) {
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Helpers::panic("CPU doesn't support EL1 32-bit mode, KVM won't work on this CPU");
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}
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// TODO: allocate these with mmap instead of malloc
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kvm_userspace_memory_region vramRegionDesc = {
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.slot = currentMemorySlot++,
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.flags = 0,
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.guest_phys_addr = PhysicalAddrs::VRAM,
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.memory_size = PhysicalAddrs::VRAMSize,
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.userspace_addr = (uint64_t)mem.getVRAM()};
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if (ioctl(vmDescriptor, KVM_SET_USER_MEMORY_REGION, &vramRegionDesc) < 0) {
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Helpers::panic("Failed to set VRAM memory region");
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}
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kvm_userspace_memory_region dspRegionDesc = {
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.slot = currentMemorySlot++,
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.flags = 0,
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.guest_phys_addr = PhysicalAddrs::DSPMem,
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.memory_size = PhysicalAddrs::DSPMemSize,
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.userspace_addr = (uint64_t)mem.getDSPMem()};
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if (ioctl(vmDescriptor, KVM_SET_USER_MEMORY_REGION, &dspRegionDesc) < 0) {
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Helpers::panic("Failed to set DSP memory region");
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}
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kvm_userspace_memory_region fcramRegionDesc = {
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.slot = currentMemorySlot++,
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.flags = 0,
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.guest_phys_addr = PhysicalAddrs::FCRAM,
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.memory_size = PhysicalAddrs::FCRAMSize * 2,
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.userspace_addr = (uint64_t)mem.getFCRAM()};
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if (ioctl(vmDescriptor, KVM_SET_USER_MEMORY_REGION, &fcramRegionDesc) < 0) {
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Helpers::panic("Failed to set FCRAM memory region");
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}
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hypervisorCodeRegion = mmap(NULL, hypervisorCodeSize, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS | MAP_NORESERVE, -1, 0);
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if (hypervisorCodeRegion == MAP_FAILED) {
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Helpers::panic("Failed to allocate memory for hypervisor I/O");
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}
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kvm_userspace_memory_region hypervisorCodeRegionDesc = {
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.slot = currentMemorySlot++,
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.flags = KVM_MEM_READONLY, // We want writes here to cause VM exits
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.guest_phys_addr = hypervisorCodeAddress,
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.memory_size = hypervisorCodeSize,
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.userspace_addr = (uint64_t)hypervisorCodeRegion
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};
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if (ioctl(vmDescriptor, KVM_SET_USER_MEMORY_REGION, &hypervisorCodeRegionDesc) < 0) {
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Helpers::panic("Failed to set up hypervisor IO memory region\n");
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return;
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}
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hypervisorDataRegion = mmap(NULL, hypervisorDataSize, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
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if (hypervisorDataRegion == MAP_FAILED) {
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Helpers::panic("Failed to allocate memory for hypervisor code");
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}
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kvm_userspace_memory_region hypervisorDataRegionDesc = {
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.slot = currentMemorySlot++,
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.flags = 0,
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.guest_phys_addr = hypervisorDataAddress,
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.memory_size = hypervisorDataSize,
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.userspace_addr = (uint64_t)hypervisorDataRegion
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};
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if (ioctl(vmDescriptor, KVM_SET_USER_MEMORY_REGION, &hypervisorDataRegionDesc) < 0) {
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Helpers::panic("Failed to set up hypervisor code memory region\n");
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return;
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}
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cpuDescriptor = ioctl(vmDescriptor, KVM_CREATE_VCPU, 0);
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if (cpuDescriptor < 0) {
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Helpers::panic("Failed to create VCPU");
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}
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int mmapSize = ioctl(kvmDescriptor, KVM_GET_VCPU_MMAP_SIZE, 0);
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if (mmapSize < 0) {
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Helpers::panic("Failed to get KVM shared memory size");
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}
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runInfo = (kvm_run*)mmap(nullptr, mmapSize, PROT_READ | PROT_WRITE, MAP_SHARED, cpuDescriptor, 0);
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if (runInfo == MAP_FAILED) {
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Helpers::panic("Failed to map KVM shared memory");
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}
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kvm_vcpu_init initParams;
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if (ioctl(vmDescriptor, KVM_ARM_PREFERRED_TARGET, &initParams) < 0) {
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Helpers::panic("Failed to fetch initialization parameters for vCPU");
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}
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initParams.features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
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initParams.features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
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if (ioctl(cpuDescriptor, KVM_ARM_VCPU_INIT, initParams) < 0) {
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Helpers::panic("Failed to initialize vCPU");
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}
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kvm_reg_list tempRegList;
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tempRegList.n = 0;
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ioctl(cpuDescriptor, KVM_GET_REG_LIST, &tempRegList);
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regList = (kvm_reg_list*)malloc(sizeof(kvm_reg_list) + tempRegList.n * sizeof(u64));
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regList->n = tempRegList.n;
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if (ioctl(cpuDescriptor, KVM_GET_REG_LIST, regList) < 0) {
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Helpers::panic("Failed to get register list");
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}
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}
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void setPC(u32 pc) {
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u64 val = (u64)pc;
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kvm_one_reg reg;
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reg.id = AARCH64_CORE_REG(regs.pc);
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reg.addr = (u64)&val;
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if (ioctl(cpuDescriptor, KVM_SET_ONE_REG, ®) < 0) [[unlikely]] {
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printf("SetPC failed\n");
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}
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}
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void run() {
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if (ioctl(cpuDescriptor, KVM_RUN, 0) < 0) {
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Helpers::panic("Failed to run vCPU");
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} else {
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printf("KVM run succeeded\n");
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}
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}
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void mapHypervisorCode(const std::vector<u8>& code, u32 offset)
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{
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if (code.size() > hypervisorCodeSize) {
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Helpers::panic("Launch code is too big");
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}
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memcpy((void*)((uintptr_t)hypervisorCodeRegion + offset), code.data(), code.size());
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}
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Memory& mem;
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Kernel& kernel;
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kvm_run* runInfo = nullptr;
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kvm_reg_list* regList = nullptr;
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void* hypervisorCodeRegion;
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void* hypervisorDataRegion;
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int kvmDescriptor = -1;
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int vmDescriptor = -1;
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int cpuDescriptor = -1;
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};
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class CPU {
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Memory& mem;
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Environment env;
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GuestState state;
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public:
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static constexpr u64 ticksPerSec = 268111856;
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CPU(Memory& mem, Kernel& kernel);
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void reset() {}
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void setReg(int index, u32 value) {}
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u32 getReg(int index) {return 0;}
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std::span<u32, 16> regs() { return state.regs; }
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std::span<u32, 32> fprs() { return state.fprs; }
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void setCPSR(u32 value) { state.cpsr = value; }
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u32 getCPSR() { return state.cpsr; }
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void setFPSCR(u32 value) { state.fpscr = value; }
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u32 getFPSCR() { return state.fpscr; }
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void setTLSBase(u32 value) {}
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u64 getTicks() {return 0;}
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u64& getTicksRef() {static u64 dummy; return dummy;}
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void clearCache() {}
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void runFrame() {}
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// TODO: remove
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void romLoaded();
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};
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#undef AARCH64_CORE_REG
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@ -17,12 +17,18 @@
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namespace PhysicalAddrs {
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enum : u32 {
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VRAM = 0x18000000,
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VRAMEnd = VRAM + 0x005FFFFF,
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VRAMSize = 0x00600000,
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VRAMEnd = VRAM + VRAMSize - 1,
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FCRAM = 0x20000000,
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FCRAMEnd = FCRAM + 0x07FFFFFF,
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DSP_RAM = 0x1FF00000,
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DSP_RAM_End = DSP_RAM + 0x0007FFFF
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DSP_RAM_End = DSP_RAM + 0x0007FFFF,
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FCRAMSize = 0x08000000,
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FCRAMEnd = FCRAM + FCRAMSize - 1,
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DSPMem = 0x1FF00000,
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DSPMemSize = 0x00080000,
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DSPMemEnd = DSPMem + DSPMemSize - 1
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};
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}
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@ -284,6 +290,7 @@ private:
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u8* getDSPDataMem() { return &dspRam[DSP_DATA_MEMORY_OFFSET]; }
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u8* getDSPCodeMem() { return &dspRam[DSP_CODE_MEMORY_OFFSET]; }
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u32 getUsedUserMem() { return usedUserMemory; }
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u8* getVRAM() { return vram; }
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void setVRAM(u8* pointer) { vram = pointer; }
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void setDSPMem(u8* pointer) { dspRam = pointer; }
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BIN
perf.data
Normal file
BIN
perf.data
Normal file
Binary file not shown.
268
src/core/CPU/cpu_kvm.cpp
Normal file
268
src/core/CPU/cpu_kvm.cpp
Normal file
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@ -0,0 +1,268 @@
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// #ifdef CPU_KVM
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#include "cpu_kvm.hpp"
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MmuTables* mmuTables = nullptr;
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// ARMv6 MMU supports up to two levels of address lookup with 4KiB pages.
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// The top level is called the level 1 table. It contains 4096 entries of 4 bytes each (16KiB total).
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// The bottom level is called level 2, which contains 256 entries of 4 bytes each (1KiB total).
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// The level 1 table supports 3 kind of entries: Pages, Sections and Supersections each corresponding to a page size.
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// Pages are for 4KiB pages, Sections are for 1MiB pages and Supersections are for 16MiB pages.
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// Sections and supersections don't use the level 2 table at all.
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// This is because with a 32 bit vaddr and 4 KiB pages, the offset is 12 bits,
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// the level 2 index is 8 bits and the level 1 index is 12 bits -> 12 + 8 + 12 = 32 for the vaddr
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// However for sections, the offset is 20 bits, so you can only use
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// the level 1 table (up to 4096 entries) because 20 for offset + 12 for level 1 -> 20 + 12 = 32 for the vaddr
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// For supersections, you need a 24 bit offset, so the level 1 table actually has up to 256 entries because
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// you're left with 8 bits -> 24 + 8 = 32 for the vaddr
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// Level 2 entries
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// Bits: 31-12 11 10 9 8-6 5-4 3 2 1 0
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// Value: BADDR nG S APX TEX[2:0] AP C B 1 XN
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// Access permission table:
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/*
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APX AP Privileged Unprivileged Description
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0 00 No access No access Permission fault
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0 01 Read/Write No access Privileged Access only
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0 10 Read/Write Read No user-mode write
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0 11 Read/Write Read/Write Full access
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1 00 - - Reserved
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1 01 Read No access Privileged Read only
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1 10 Read Read Read only
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1 11 - - Reserved
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*/
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constexpr u32 APX = 1 << 9;
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constexpr u32 AP0 = 1 << 4;
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constexpr u32 AP1 = 1 << 5;
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enum Level2Flags : u32
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{
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Level2Flags_ExecuteNever = 1 << 0,
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Level2Flags_Bufferable = 1 << 2,
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Level2Flags_Cacheable = 1 << 3,
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Level2Flags_Shared = 1 << 10,
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Level2Flags_AP_NoUserModeWrite = AP1,
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Level2Flags_AP_FullAccess = AP1 | AP0,
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};
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// Generated by passing the following code to godbolt:
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// Thanks libn3ds
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/*
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// FCSE PID Register (FCSE PID = 0)
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// Note: This must be 0 before disabling the MMU otherwise UB
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__asm__ volatile ("mcr p15, 0, %0, c13, c0, 0" : : "r"(0));
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// Context ID Register (ASID = 0, PROCID = 0)
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__asm__ volatile ("mcr p15, 0, %0, c13, c0, 1" : : "r"(0));
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// // TTBR0 address shared page table walk and outer cachable write-through, no allocate on write
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uint32_t ttbr0 = mmuTableAddress | 0x12;
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__asm__ volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0) : "memory");
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// Use the 16 KiB L1 table only
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__asm__ volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r"(0));
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// Domain 0 = client, remaining domains all = no access
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__asm__ volatile("mcr p15, 0, %0, c3, c0, 0" : : "r"(1));
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uint32_t* d = (uint32_t*)hypervisorCodeAddress;
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*d = hypervisorCodeAddress;
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*/
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constexpr u8 mmuCodeBefore[] = {
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0x00, 0x30, 0xb0, 0xe3, // movs r3, #0
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0x10, 0x3f, 0x0d, 0xee, // mcr p15, #0, r3, c13, c0, #0
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0x30, 0x3f, 0x0d, 0xee, // mcr p15, #0, r3, c13, c0, #1
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0x14, 0x20, 0x9f, 0xe5, // ldr r2, [pc, #0x14]
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0x10, 0x2f, 0x02, 0xee, // mcr p15, #0, r2, c2, c0, #0
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0x50, 0x3f, 0x02, 0xee, // mcr p15, #0, r3, c2, c0, #2
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0x01, 0x30, 0xb0, 0xe3, // movs r3, #1
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0x10, 0x3f, 0x03, 0xee, // mcr p15, #0, r3, c3, c0, #0
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0x0d, 0x32, 0xa0, 0xe3, // mov r3, #-0x30000000 TODO: instead jump to exit code
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0x00, 0x30, 0x83, 0xe5, // str r3, [r3]
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(mmuTableAddress & 0xFF) | 0x12, (mmuTableAddress >> 8) & 0xFF, (mmuTableAddress >> 16) & 0xFF, (mmuTableAddress >> 24) & 0xFF,
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};
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// Generated by passing the following code to godbolt:
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// Thanks libn3ds
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/*
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// Invalidate TLB
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__asm__ volatile("mcr p15, 0, %0, c8, c7, 0" : : "r"(0));
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__asm__ volatile("dsb");
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// Get ACR
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uint32_t reg;
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__asm__ volatile("mrc p15, 0, %0, c1, c0, 1" : "=r"(reg));
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// Enable Return stack, Dynamic branch prediction, Static branch prediction,
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// Instruction folding and SMP mode: the CPU is taking part in coherency
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reg |= 0x2F;
|
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__asm__ volatile("mcr p15, 0, %0, c1, c0, 1" : : "r"(reg));
|
||||
|
||||
// Get CR
|
||||
__asm__ volatile("mrc p15, 0, %0, c1, c0, 0" : "=r"(reg));
|
||||
// Enable MMU, D-Cache, Program flow prediction,
|
||||
// I-Cache, high exception vectors, Unaligned data access,
|
||||
// subpage AP bits disabled
|
||||
reg |= 0xC03805;
|
||||
__asm__ volatile("mcr p15, 0, %0, c1, c0, 0" : : "r"(reg));
|
||||
|
||||
// Invalidate both caches
|
||||
__asm__ volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (0) : "memory");
|
||||
__asm__ volatile("dsb");
|
||||
__asm__ volatile("isb");
|
||||
|
||||
uint32_t* d = (uint32_t*)hypervisorCodeAddress;
|
||||
*d = hypervisorCodeAddress;
|
||||
*/
|
||||
constexpr u8 mmuCodeAfter[] = {
|
||||
0x00, 0x00, 0xb0, 0xe3, // movs r0, #0
|
||||
0x17, 0x0f, 0x08, 0xee, // mcr p15, #0, r0, c8, c7, #0
|
||||
0x4f, 0xf0, 0x7f, 0xf5, // dsb sy
|
||||
0x30, 0x3f, 0x11, 0xee, // mrc p15, #0, r3, c1, c0, #1
|
||||
0x2f, 0x30, 0x83, 0xe3, // orr r3, r3, #0x2f
|
||||
0x30, 0x3f, 0x01, 0xee, // mcr p15, #0, r3, c1, c0, #1
|
||||
0x10, 0x2f, 0x11, 0xee, // mrc p15, #0, r2, c1, c0, #0
|
||||
0x05, 0x38, 0x03, 0xe3, // movw r3, #0x3805
|
||||
0xc0, 0x30, 0x40, 0xe3, // movt r3, #0xc0
|
||||
0x02, 0x30, 0x93, 0xe1, // orrs r3, r3, r2
|
||||
0x10, 0x3f, 0x01, 0xee, // mcr p15, #0, r3, c1, c0, #0
|
||||
0x17, 0x0f, 0x07, 0xee, // mcr p15, #0, r0, c7, c7, #0
|
||||
0x4f, 0xf0, 0x7f, 0xf5, // dsb sy
|
||||
0x6f, 0xf0, 0x7f, 0xf5, // isb sy
|
||||
0x0d, 0x32, 0xa0, 0xe3, // mov r3, #-0x30000000 TODO: instead jump to exit code
|
||||
0x00, 0x30, 0x83, 0xe5, // str r3, [r3]
|
||||
};
|
||||
|
||||
// Store the CPU state and exit the VM, then return from SVC
|
||||
// Generated from the following ARM32 assembly
|
||||
/*
|
||||
push {r0}
|
||||
ldr r0, GuestStateAddr + 4
|
||||
stmfd r0, {r1-r12, sp, lr, pc}^
|
||||
pop {r0}
|
||||
|
||||
push {r1}
|
||||
ldr r1, GuestStateAddr
|
||||
str r0, [r1]
|
||||
|
||||
// Exit the VM
|
||||
ldr r1, CodeAddr
|
||||
str r1, [r1]
|
||||
|
||||
pop {r1}
|
||||
|
||||
CodeAddr:
|
||||
.word 0xD0000000
|
||||
GuestStateAddr:
|
||||
.word 0xE0200000
|
||||
*/
|
||||
constexpr u8 svcHandlerCode[] = {
|
||||
};
|
||||
|
||||
/// Level 1, page table entry
|
||||
/// Bits: 31-10 9 8-5 4 3 2 1 0
|
||||
/// Value: BADDR IMP Domain SBZ NS PXN 0 1
|
||||
/// We don't use domains, so we can set it to 0
|
||||
u32 pageTableEntry(u32 level2Address)
|
||||
{
|
||||
// Level 2 tables have 256 entries of 4 bytes each, so they must be aligned to 1KiB
|
||||
if ((level2Address & 0x3FF) != 0) {
|
||||
Helpers::panic("level2Address is not aligned to 1KiB");
|
||||
}
|
||||
|
||||
return level2Address | 0b1;
|
||||
}
|
||||
|
||||
u32 level2Entry(u32 physicalAddress, Level2Flags flags)
|
||||
{
|
||||
return (physicalAddress & 0xFFFFF000) | 0b10 | flags;
|
||||
}
|
||||
|
||||
void mapPageTables(u32 virtualAddress, u32 physicalAddress, u8 pageCount, Level2Flags flags)
|
||||
{
|
||||
if ((virtualAddress & 0xFFFFF000) != 0) {
|
||||
Helpers::panic("virtualAddress is not aligned to 4KiB");
|
||||
}
|
||||
|
||||
if ((physicalAddress & 0xFFFFF000) != 0) {
|
||||
Helpers::panic("physicalAddress is not aligned to 4KiB");
|
||||
}
|
||||
|
||||
for (u32 i = 0; i < pageCount * 4096; i += 4096)
|
||||
{
|
||||
u8 level2Index = ((virtualAddress + i) >> 12) & 0xFF;
|
||||
mmuTables->level2SectionTables[level2Index] = level2Entry(physicalAddress + i, flags);
|
||||
}
|
||||
|
||||
u32 level2TableAddressVm = mmuTableAddress + offsetof(MmuTables, level2SectionTables);
|
||||
mmuTables->level1[virtualAddress >> 20] = pageTableEntry(level2TableAddressVm);
|
||||
}
|
||||
|
||||
CPU::CPU(Memory& mem, Kernel& kernel)
|
||||
: mem(mem), env(mem, kernel)
|
||||
{
|
||||
}
|
||||
|
||||
void CPU::romLoaded()
|
||||
{
|
||||
NCCH* ncch = mem.getCXI();
|
||||
if (!ncch) {
|
||||
// TODO: what to do here?
|
||||
Helpers::panic("Alber has decided to panic!");
|
||||
}
|
||||
|
||||
// Map the VM exit code which stores all registers to shared hypervisor memory
|
||||
// and exits the VM by writing to read-only memory.
|
||||
// We map it at the start of hypervisorCodeAddress.
|
||||
env.mapHypervisorCode(std::vector<u8>(vmExitCode, vmExitCode + sizeof(vmExitCode)), 0);
|
||||
|
||||
printf("Debug: Running pre mmu table code\n");
|
||||
env.mapHypervisorCode(std::vector<u8>(mmuCodeBefore, mmuCodeBefore + sizeof(mmuCodeBefore)), customEntryOffset);
|
||||
env.setPC(hypervisorCodeAddress + customEntryOffset);
|
||||
env.run();
|
||||
|
||||
const auto& text = ncch->text;
|
||||
const auto& rodata = ncch->rodata;
|
||||
const auto& data = ncch->data;
|
||||
|
||||
mmuTables = (MmuTables*)((uintptr_t)env.hypervisorDataRegion + mmuTableOffset);
|
||||
printf("Debug: level2sectionTables is at %p in host, %08x in guest\n", mmuTables->level2SectionTables, mmuTableAddress + offsetof(MmuTables, level2SectionTables));
|
||||
mapPageTables(
|
||||
text.address,
|
||||
text.address,
|
||||
text.pageCount,
|
||||
(Level2Flags)(Level2Flags_Shared |
|
||||
Level2Flags_Bufferable |
|
||||
Level2Flags_Cacheable |
|
||||
Level2Flags_AP_NoUserModeWrite)
|
||||
);
|
||||
mapPageTables(
|
||||
rodata.address,
|
||||
rodata.address,
|
||||
rodata.pageCount,
|
||||
(Level2Flags)(Level2Flags_Shared |
|
||||
Level2Flags_Bufferable |
|
||||
Level2Flags_Cacheable |
|
||||
Level2Flags_AP_NoUserModeWrite |
|
||||
Level2Flags_ExecuteNever)
|
||||
);
|
||||
mapPageTables(
|
||||
data.address,
|
||||
data.address,
|
||||
data.pageCount,
|
||||
(Level2Flags)(Level2Flags_Shared |
|
||||
Level2Flags_Bufferable |
|
||||
Level2Flags_Cacheable |
|
||||
Level2Flags_AP_FullAccess)
|
||||
);
|
||||
|
||||
printf("Debug: Running post mmu table code\n");
|
||||
env.mapHypervisorCode(std::vector<u8>(mmuCodeAfter, mmuCodeAfter + sizeof(mmuCodeAfter)), customEntryOffset);
|
||||
env.setPC(hypervisorCodeAddress + customEntryOffset);
|
||||
env.run();
|
||||
printf("Done\n");
|
||||
}
|
||||
|
||||
// #endif
|
||||
Loading…
Add table
Reference in a new issue