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WIP arm64 shader recompiler
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wheremyfoodat
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281a7eefbf
commit
c0621d0760
7 changed files with 383 additions and 4 deletions
239
src/core/PICA/dynapica/shader_rec_emitter_arm64.cpp
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239
src/core/PICA/dynapica/shader_rec_emitter_arm64.cpp
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#if defined(PANDA3DS_DYNAPICA_SUPPORTED) && defined(PANDA3DS_ARM64_HOST)
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#include "PICA/dynapica/shader_rec_emitter_arm64.hpp"
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#include <bit>
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using namespace Helpers;
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using namespace oaknut;
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using namespace oaknut::util;
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// Similar to the x64 recompiler, we use an odd internal ABI, which abuses the fact that we'll very rarely be calling C++ functions
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// So to avoid pushing and popping, we'll be making use of volatile registers as much as possible
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static constexpr QReg scratch1 = Q0;
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static constexpr QReg scratch2 = Q1;
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static constexpr QReg src1_vec = Q2;
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static constexpr QReg src2_vec = Q3;
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static constexpr QReg src3_vec = Q4;
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static constexpr XReg statePointer = X9;
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void ShaderEmitter::compile(const PICAShader& shaderUnit) {
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// Scan the code for call, exp2, log2, etc instructions which need some special care
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// After that, emit exp2 and log2 functions if the corresponding instructions are present
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scanCode(shaderUnit);
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if (codeHasExp2) Helpers::panic("arm64 shader JIT: Code has exp2");
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if (codeHasLog2) Helpers::panic("arm64 shader JIT: Code has log2");
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align(16);
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// Compile every instruction in the shader
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// This sounds horrible but the PICA instruction memory is tiny, and most of the time it's padded wtih nops that compile to nothing
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recompilerPC = 0;
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loopLevel = 0;
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compileUntil(shaderUnit, PICAShader::maxInstructionCount);
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}
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void ShaderEmitter::scanCode(const PICAShader& shaderUnit) {
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returnPCs.clear();
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for (u32 i = 0; i < PICAShader::maxInstructionCount; i++) {
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const u32 instruction = shaderUnit.loadedShader[i];
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const u32 opcode = instruction >> 26;
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if (isCall(instruction)) {
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const u32 num = instruction & 0xff;
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const u32 dest = getBits<10, 12>(instruction);
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const u32 returnPC = num + dest; // Add them to get the return PC
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returnPCs.push_back(returnPC);
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} else if (opcode == ShaderOpcodes::EX2) {
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codeHasExp2 = true;
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} else if (opcode == ShaderOpcodes::LG2) {
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codeHasLog2 = true;
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}
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}
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// Sort return PCs so they can be binary searched
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std::sort(returnPCs.begin(), returnPCs.end());
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}
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void ShaderEmitter::compileUntil(const PICAShader& shaderUnit, u32 end) {
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while (recompilerPC < end) {
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compileInstruction(shaderUnit);
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}
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}
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void ShaderEmitter::compileInstruction(const PICAShader& shaderUnit) {
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// Write current location to label for this instruction
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l(instructionLabels[recompilerPC]);
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// See if PC is a possible return PC and emit the proper code if so
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if (std::binary_search(returnPCs.begin(), returnPCs.end(), recompilerPC)) {
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Helpers::panic("Unimplemented return address for call instruction");
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}
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// Fetch instruction and inc PC
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const u32 instruction = shaderUnit.loadedShader[recompilerPC++];
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const u32 opcode = instruction >> 26;
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switch (opcode) {
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// case ShaderOpcodes::ADD: recADD(shaderUnit, instruction); break;
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// case ShaderOpcodes::CALL: recCALL(shaderUnit, instruction); break;
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// case ShaderOpcodes::CALLC: recCALLC(shaderUnit, instruction); break;
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// case ShaderOpcodes::CALLU: recCALLU(shaderUnit, instruction); break;
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// case ShaderOpcodes::CMP1:
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// case ShaderOpcodes::CMP2: recCMP(shaderUnit, instruction); break;
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// case ShaderOpcodes::DP3: recDP3(shaderUnit, instruction); break;
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// case ShaderOpcodes::DP4: recDP4(shaderUnit, instruction); break;
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// case ShaderOpcodes::DPH:
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// case ShaderOpcodes::DPHI: recDPH(shaderUnit, instruction); break;
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// case ShaderOpcodes::END: recEND(shaderUnit, instruction); break;
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// case ShaderOpcodes::EX2: recEX2(shaderUnit, instruction); break;
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// case ShaderOpcodes::FLR: recFLR(shaderUnit, instruction); break;
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// case ShaderOpcodes::IFC: recIFC(shaderUnit, instruction); break;
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// case ShaderOpcodes::IFU: recIFU(shaderUnit, instruction); break;
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// case ShaderOpcodes::JMPC: recJMPC(shaderUnit, instruction); break;
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// case ShaderOpcodes::JMPU: recJMPU(shaderUnit, instruction); break;
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// case ShaderOpcodes::LG2: recLG2(shaderUnit, instruction); break;
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// case ShaderOpcodes::LOOP: recLOOP(shaderUnit, instruction); break;
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case ShaderOpcodes::MOV: recMOV(shaderUnit, instruction); break;
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// case ShaderOpcodes::MOVA: recMOVA(shaderUnit, instruction); break;
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// case ShaderOpcodes::MAX: recMAX(shaderUnit, instruction); break;
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// case ShaderOpcodes::MIN: recMIN(shaderUnit, instruction); break;
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// case ShaderOpcodes::MUL: recMUL(shaderUnit, instruction); break;
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case ShaderOpcodes::NOP:
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break;
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// case ShaderOpcodes::RCP: recRCP(shaderUnit, instruction); break;
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// case ShaderOpcodes::RSQ: recRSQ(shaderUnit, instruction); break;
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// Unimplemented opcodes that don't seem to actually be used but exist in the binary
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// EMIT/SETEMIT are used in geometry shaders, however are sometimes found in vertex shaders?
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// case ShaderOpcodes::EMIT:
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// case ShaderOpcodes::SETEMIT:
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// log("[ShaderJIT] Unknown PICA opcode: %02X\n", opcode);
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// emitPrintLog(shaderUnit);
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// break;
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// case ShaderOpcodes::BREAK:
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// case ShaderOpcodes::BREAKC: Helpers::warn("[Shader JIT] Unimplemented BREAK(C) instruction!"); break;
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// We consider both MAD and MADI to be the same instruction and decode which one we actually have in recMAD
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// case 0x30:
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// case 0x31:
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// case 0x32:
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// case 0x33:
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// case 0x34:
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// case 0x35:
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// case 0x36:
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// case 0x37:
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// case 0x38:
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// case 0x39:
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// case 0x3A:
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// case 0x3B:
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// case 0x3C:
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// case 0x3D:
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// case 0x3E:
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// case 0x3F: recMAD(shaderUnit, instruction); break;
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// case ShaderOpcodes::SLT:
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// case ShaderOpcodes::SLTI: recSLT(shaderUnit, instruction); break;
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// case ShaderOpcodes::SGE:
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// case ShaderOpcodes::SGEI: recSGE(shaderUnit, instruction); break;
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default: Helpers::panic("Shader JIT: Unimplemented PICA opcode %X", opcode);
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}
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}
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const ShaderEmitter::vec4f& ShaderEmitter::getSourceRef(const PICAShader& shader, u32 src) {
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if (src < 0x10)
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return shader.inputs[src];
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else if (src < 0x20)
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return shader.tempRegisters[src - 0x10];
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else if (src <= 0x7f)
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return shader.floatUniforms[src - 0x20];
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else {
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Helpers::warn("[Shader JIT] Unimplemented source value: %X\n", src);
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return shader.dummy;
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}
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}
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const ShaderEmitter::vec4f& ShaderEmitter::getDestRef(const PICAShader& shader, u32 dest) {
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if (dest < 0x10) {
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return shader.outputs[dest];
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} else if (dest < 0x20) {
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return shader.tempRegisters[dest - 0x10];
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}
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Helpers::panic("[Shader JIT] Unimplemented dest: %X", dest);
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}
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// See shader.hpp header for docs on how the swizzle and negate works
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template <int sourceIndex>
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void ShaderEmitter::loadRegister(QReg dest, const PICAShader& shader, u32 src, u32 index, u32 operandDescriptor) {
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u32 compSwizzle; // Component swizzle pattern for the register
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bool negate; // If true, negate all lanes of the register
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if constexpr (sourceIndex == 1) { // SRC1
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negate = (getBit<4>(operandDescriptor)) != 0;
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compSwizzle = getBits<5, 8>(operandDescriptor);
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} else if constexpr (sourceIndex == 2) { // SRC2
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negate = (getBit<13>(operandDescriptor)) != 0;
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compSwizzle = getBits<14, 8>(operandDescriptor);
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} else if constexpr (sourceIndex == 3) { // SRC3
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negate = (getBit<22>(operandDescriptor)) != 0;
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compSwizzle = getBits<23, 8>(operandDescriptor);
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}
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switch (index) {
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case 0:
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[[likely]] { // Keep src as is, no need to offset it
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const vec4f& srcRef = getSourceRef(shader, src);
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const uintptr_t offset = uintptr_t(&srcRef) - uintptr_t(&shader); // Calculate offset of register from start of the state struct
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LDR(dest, statePointer, offset);
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switch (compSwizzle) {
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case noSwizzle: break; // .xyzw
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case 0x0: DUP(dest.S4(), dest.Selem()[0]); break; // .xxxx
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case 0x55: DUP(dest.S4(), dest.Selem()[1]); break; // .yyyy
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case 0xAA: DUP(dest.S4(), dest.Selem()[2]); break; // .zzzz
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case 0xFF: DUP(dest.S4(), dest.Selem()[3]); break; // .wwww
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default: Helpers::panic("Unimplemented swizzle pattern for loading");
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}
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// Negate the register if necessary
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if (negate) {
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FNEG(dest.S4(), dest.S4());
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}
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return; // Return. Rest of the function handles indexing which is not used if index == 0
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}
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default: Helpers::panic("[ShaderJIT]: Unimplemented source index type %d", index);
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}
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Helpers::panic("Unimplemented indexed register load");
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}
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void ShaderEmitter::storeRegister(QReg source, const PICAShader& shader, u32 dest, u32 operandDescriptor) {
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const vec4f& destRef = getDestRef(shader, dest);
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const uintptr_t offset = uintptr_t(&destRef) - uintptr_t(&shader); // Calculate offset of register from start of the state struct
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// Mask of which lanes to write
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u32 writeMask = operandDescriptor & 0xf;
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if (writeMask == 0xf) { // No lanes are masked, just use STR
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STR(source, statePointer, offset);
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} else {
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LDR(scratch1, statePointer, offset); // Load current source
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Helpers::panic("Unimplemented: Storing to register with blending");
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}
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}
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void ShaderEmitter::recMOV(const PICAShader& shader, u32 instruction) {
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const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];
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const u32 src = getBits<12, 7>(instruction);
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const u32 idx = getBits<19, 2>(instruction);
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const u32 dest = getBits<21, 5>(instruction);
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loadRegister<1>(src1_vec, shader, src, idx, operandDescriptor); // Load source 1 into scratch1
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storeRegister(src1_vec, shader, dest, operandDescriptor);
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}
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#endif
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@ -342,10 +342,10 @@ void ShaderEmitter::storeRegister(Xmm source, const PICAShader& shader, u32 dest
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} else if (std::popcount(writeMask) == 1) { // Only 1 register needs to be written back. This can be done with a simple shift right + movss
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int bit = std::countr_zero(writeMask); // Get which PICA register needs to be written to (0 = w, 1 = z, etc)
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size_t index = 3 - bit;
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const uintptr_t lane_offset = offset + index * sizeof(float);
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const uintptr_t laneOffset = offset + index * sizeof(float);
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if (index == 0) { // Bottom lane, no need to shift
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movss(dword[statePointer + lane_offset], source);
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movss(dword[statePointer + laneOffset], source);
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} else { // Shift right by 32 * index, then write bottom lane
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if (haveAVX) {
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vpsrldq(scratch1, source, index * sizeof(float));
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@ -353,7 +353,7 @@ void ShaderEmitter::storeRegister(Xmm source, const PICAShader& shader, u32 dest
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movaps(scratch1, source);
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psrldq(scratch1, index * sizeof(float));
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}
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movss(dword[statePointer + lane_offset], scratch1);
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movss(dword[statePointer + laneOffset], scratch1);
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}
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} else if (haveSSE4_1) {
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// Bit reverse the write mask because that is what blendps expects
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