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[Shader JIT] Implement SGE(I)

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wheremyfoodat 2023-08-02 19:30:35 +03:00
parent 3d5f1ea517
commit f73138c5de
3 changed files with 23 additions and 1 deletions
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1
include/PICA/dynapica/shader_rec_emitter_x64.hpp
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@ -112,7 +112,6 @@ class ShaderEmitter : public Xbyak::CodeGenerator {
void recRSQ(const PICAShader& shader, u32 instruction); void recRSQ(const PICAShader& shader, u32 instruction);
void recSETEMIT(const PICAShader& shader, u32 instruction); void recSETEMIT(const PICAShader& shader, u32 instruction);
void recSGE(const PICAShader& shader, u32 instruction); void recSGE(const PICAShader& shader, u32 instruction);
void recSGEI(const PICAShader& shader, u32 instruction);
void recSLT(const PICAShader& shader, u32 instruction); void recSLT(const PICAShader& shader, u32 instruction);
MAKE_LOG_FUNCTION(log, shaderJITLogger) MAKE_LOG_FUNCTION(log, shaderJITLogger)

1
include/PICA/shader.hpp
View file

@ -23,6 +23,7 @@ namespace ShaderOpcodes {
LG2 = 0x06, LG2 = 0x06,
LIT = 0x07, LIT = 0x07,
MUL = 0x08, MUL = 0x08,
SGE = 0x09,
SLT = 0x0A, SLT = 0x0A,
FLR = 0x0B, FLR = 0x0B,
MAX = 0x0C, MAX = 0x0C,

22
src/core/PICA/dynapica/shader_rec_emitter_x64.cpp
View file

@ -180,6 +180,10 @@ void ShaderEmitter::compileInstruction(const PICAShader& shaderUnit) {
case ShaderOpcodes::SLTI: case ShaderOpcodes::SLTI:
recSLT(shaderUnit, instruction); break; recSLT(shaderUnit, instruction); break;
case ShaderOpcodes::SGE:
case ShaderOpcodes::SGEI:
recSGE(shaderUnit, instruction); break;
default: default:
Helpers::panic("Shader JIT: Unimplemented PICA opcode %X", opcode); Helpers::panic("Shader JIT: Unimplemented PICA opcode %X", opcode);
} }
@ -681,6 +685,24 @@ void ShaderEmitter::recSLT(const PICAShader& shader, u32 instruction) {
storeRegister(src1_xmm, shader, dest, operandDescriptor); storeRegister(src1_xmm, shader, dest, operandDescriptor);
} }
void ShaderEmitter::recSGE(const PICAShader& shader, u32 instruction) {
const bool isSGEI = (instruction >> 26) == ShaderOpcodes::SGEI;
const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];
const u32 src1 = isSGEI ? getBits<14, 5>(instruction) : getBits<12, 7>(instruction);
const u32 src2 = isSGEI ? getBits<7, 7>(instruction) : getBits<7, 5>(instruction);
const u32 idx = getBits<19, 2>(instruction);
const u32 dest = getBits<21, 5>(instruction);
loadRegister<1>(src1_xmm, shader, src1, isSGEI ? 0 : idx, operandDescriptor);
loadRegister<2>(src2_xmm, shader, src2, isSGEI ? idx : 0, operandDescriptor);
// SSE does not have a cmpgeps instruction so we turn src1 >= src2 to src2 <= src1, result in src2
cmpleps(src2_xmm, src1_xmm);
andps(src2_xmm, xword[rip + onesVector]);
storeRegister(src2_xmm, shader, dest, operandDescriptor);
}
void ShaderEmitter::recCMP(const PICAShader& shader, u32 instruction) { void ShaderEmitter::recCMP(const PICAShader& shader, u32 instruction) {
const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f]; const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];
const u32 src1 = getBits<12, 7>(instruction); const u32 src1 = getBits<12, 7>(instruction);