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code: Better screen support

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GPUCode 2023-07-10 23:59:44 +03:00
parent d28796fd3f
commit f75a23b5a9
15 changed files with 305 additions and 66 deletions
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27
src/core/PICA/gpu.cpp
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@ -16,6 +16,12 @@
#include "renderer_vk/renderer_vk.hpp"
#endif
constexpr u32 top_screen_width = 240;
constexpr u32 top_screen_height = 400;
constexpr u32 bottom_screen_width = 240;
constexpr u32 bottom_screen_height = 300;
using namespace Floats;
// Note: For when we have multiple backends, the GL state manager can stay here and have the constructor for the Vulkan-or-whatever renderer ignore it
@ -78,6 +84,27 @@ void GPU::reset() {
e.config2 = 0;
}
// Initialize the framebuffer registers. Values taken from Citra.
using namespace PICA::ExternalRegs;
// Top screen addresses and dimentions.
external_regs[Framebuffer0AFirstAddr] = 0x181E6000;
external_regs[Framebuffer0ASecondAddr] = 0x1822C800;
external_regs[Framebuffer0BFirstAddr] = 0x18273000;
external_regs[Framebuffer0BSecondAddr] = 0x182B9800;
external_regs[Framebuffer0Size] = (top_screen_height << 16) | top_screen_width;
external_regs[Framebuffer0Stride] = 720;
external_regs[Framebuffer0Config] = static_cast<u32>(PICA::ColorFmt::RGB8);
external_regs[Framebuffer0Select] = 0;
// Bottom screen addresses and dimentions.
external_regs[Framebuffer1AFirstAddr] = 0x1848F000;
external_regs[Framebuffer1ASecondAddr] = 0x184C7800;
external_regs[Framebuffer1Size] = (bottom_screen_height << 16) | bottom_screen_width;
external_regs[Framebuffer1Stride] = 720;
external_regs[Framebuffer1Config] = static_cast<u32>(PICA::ColorFmt::RGB8);
external_regs[Framebuffer1Select] = 0;
renderer->reset();
}

31
src/core/PICA/regs.cpp
View file

@ -19,11 +19,36 @@ void GPU::writeReg(u32 address, u32 value) {
if (address >= 0x1EF01000 && address < 0x1EF01C00) { // Internal registers
const u32 index = (address - 0x1EF01000) / sizeof(u32);
writeInternalReg(index, value, 0xffffffff);
} else if (address >= 0x1EF00004 && address < 0x1EF01000) {
const u32 index = (address - 0x1EF00004) / sizeof(u32);
writeExternalReg(index, value);
} else {
log("Ignoring write to external GPU register %08X. Value: %08X\n", address, value);
log("Ignoring write to unknown GPU register %08X. Value: %08X\n", address, value);
}
}
u32 GPU::readExternalReg(u32 index) {
using namespace PICA::ExternalRegs;
if (index > 0x1000) [[unlikely]] {
Helpers::panic("Tried to read invalid external GPU register. Index: %X\n", index);
return -1;
}
return external_regs[index];
}
void GPU::writeExternalReg(u32 index, u32 value) {
using namespace PICA::ExternalRegs;
if (index > 0x1000) [[unlikely]] {
Helpers::panic("Tried to write to invalid external GPU register. Index: %X, value: %08X\n", index, value);
return;
}
external_regs[index] = value;
}
u32 GPU::readInternalReg(u32 index) {
using namespace PICA::InternalRegs;
@ -162,7 +187,7 @@ void GPU::writeInternalReg(u32 index, u32 value, u32 mask) {
}
break;
// Restart immediate mode primitive drawing
// Restart immediate mode primitive drawing
case PrimitiveRestart:
if (value & 1) {
immediateModeAttrIndex = 0;
@ -384,4 +409,4 @@ void GPU::startCommandList(u32 addr, u32 size) {
writeInternalReg(id, param, mask);
}
}
}
}