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https://github.com/wheremyfoodat/Panda3DS.git
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Get some demos running on a64 shader JIT
This commit is contained in:
wheremyfoodat
parent
c0621d0760
commit
fe01df588b
2 changed files with 236 additions and 42 deletions
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@ -27,6 +27,9 @@ class ShaderEmitter : private oaknut::CodeBlock, public oaknut::CodeGenerator {
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// Filled before compiling a shader by scanning the code for call instructions
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std::vector<u32> returnPCs;
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// An array of 128-bit masks for blending registers together to perform masked writes.
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// Eg for writing only the x and y components, the mask is 0x00000000'00000000'FFFFFFFF'FFFF
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oaknut::Label blendMasks;
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// Vector value of (1.0, 1.0, 1.0, 1.0) for SLT(i)/SGE(i)
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oaknut::Label onesVector;
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@ -15,9 +15,37 @@ static constexpr QReg src1_vec = Q2;
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static constexpr QReg src2_vec = Q3;
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static constexpr QReg src3_vec = Q4;
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static constexpr XReg arg1 = X0;
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static constexpr XReg arg2 = X1;
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static constexpr XReg statePointer = X9;
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void ShaderEmitter::compile(const PICAShader& shaderUnit) {
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oaknut::CodeBlock::unprotect(); // Unprotect the memory before writing to it
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// Constants
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align(16);
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// Generate blending masks for doing masked writes to registers
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l(blendMasks);
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for (int i = 0; i < 16; i++) {
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dw((i & 0x8) ? 0xFFFFFFFF : 0); // Mask for x component
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dw((i & 0x4) ? 0xFFFFFFFF : 0); // Mask for y component
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dw((i & 0x2) ? 0xFFFFFFFF : 0); // Mask for z component
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dw((i & 0x1) ? 0xFFFFFFFF : 0); // Mask for w component
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}
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// Emit prologue first
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oaknut::Label prologueLabel;
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align(16);
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l(prologueLabel);
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prologueCb = prologueLabel.ptr<PrologueCallback>();
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// Set state pointer to the proper pointer
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// state pointer is volatile, no need to preserve it
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MOV(statePointer, arg1);
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// Jump to code with a tail call
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BR(arg2);
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// Scan the code for call, exp2, log2, etc instructions which need some special care
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// After that, emit exp2 and log2 functions if the corresponding instructions are present
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scanCode(shaderUnit);
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@ -30,6 +58,10 @@ void ShaderEmitter::compile(const PICAShader& shaderUnit) {
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recompilerPC = 0;
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loopLevel = 0;
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compileUntil(shaderUnit, PICAShader::maxInstructionCount);
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// Protect the memory and invalidate icache before executing the code
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oaknut::CodeBlock::protect();
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oaknut::CodeBlock::invalidate_all();
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}
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void ShaderEmitter::scanCode(const PICAShader& shaderUnit) {
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@ -76,17 +108,17 @@ void ShaderEmitter::compileInstruction(const PICAShader& shaderUnit) {
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const u32 opcode = instruction >> 26;
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switch (opcode) {
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// case ShaderOpcodes::ADD: recADD(shaderUnit, instruction); break;
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case ShaderOpcodes::ADD: recADD(shaderUnit, instruction); break;
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// case ShaderOpcodes::CALL: recCALL(shaderUnit, instruction); break;
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// case ShaderOpcodes::CALLC: recCALLC(shaderUnit, instruction); break;
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// case ShaderOpcodes::CALLU: recCALLU(shaderUnit, instruction); break;
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// case ShaderOpcodes::CMP1:
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// case ShaderOpcodes::CMP2: recCMP(shaderUnit, instruction); break;
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// case ShaderOpcodes::DP3: recDP3(shaderUnit, instruction); break;
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// case ShaderOpcodes::DP4: recDP4(shaderUnit, instruction); break;
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case ShaderOpcodes::DP3: recDP3(shaderUnit, instruction); break;
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case ShaderOpcodes::DP4: recDP4(shaderUnit, instruction); break;
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// case ShaderOpcodes::DPH:
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// case ShaderOpcodes::DPHI: recDPH(shaderUnit, instruction); break;
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// case ShaderOpcodes::END: recEND(shaderUnit, instruction); break;
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case ShaderOpcodes::END: recEND(shaderUnit, instruction); break;
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// case ShaderOpcodes::EX2: recEX2(shaderUnit, instruction); break;
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// case ShaderOpcodes::FLR: recFLR(shaderUnit, instruction); break;
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// case ShaderOpcodes::IFC: recIFC(shaderUnit, instruction); break;
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@ -97,42 +129,43 @@ void ShaderEmitter::compileInstruction(const PICAShader& shaderUnit) {
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// case ShaderOpcodes::LOOP: recLOOP(shaderUnit, instruction); break;
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case ShaderOpcodes::MOV: recMOV(shaderUnit, instruction); break;
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// case ShaderOpcodes::MOVA: recMOVA(shaderUnit, instruction); break;
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// case ShaderOpcodes::MAX: recMAX(shaderUnit, instruction); break;
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// case ShaderOpcodes::MIN: recMIN(shaderUnit, instruction); break;
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// case ShaderOpcodes::MUL: recMUL(shaderUnit, instruction); break;
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case ShaderOpcodes::NOP:
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case ShaderOpcodes::MAX: recMAX(shaderUnit, instruction); break;
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case ShaderOpcodes::MIN: recMIN(shaderUnit, instruction); break;
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case ShaderOpcodes::MUL: recMUL(shaderUnit, instruction); break;
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case ShaderOpcodes::NOP: break;
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// case ShaderOpcodes::RCP: recRCP(shaderUnit, instruction); break;
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case ShaderOpcodes::RSQ: recRSQ(shaderUnit, instruction); break;
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// Unimplemented opcodes that don't seem to actually be used but exist in the binary
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// EMIT/SETEMIT are used in geometry shaders, however are sometimes found in vertex shaders?
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// case ShaderOpcodes::EMIT:
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// case ShaderOpcodes::SETEMIT:
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// log("[ShaderJIT] Unknown PICA opcode: %02X\n", opcode);
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// emitPrintLog(shaderUnit);
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// break;
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// case ShaderOpcodes::BREAK:
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// case ShaderOpcodes::BREAKC: Helpers::warn("[Shader JIT] Unimplemented BREAK(C) instruction!"); break;
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// We consider both MAD and MADI to be the same instruction and decode which one we actually have in recMAD
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case 0x30:
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case 0x31:
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case 0x32:
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case 0x33:
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case 0x34:
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case 0x35:
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case 0x36:
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case 0x37:
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case 0x38:
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case 0x39:
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case 0x3A:
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case 0x3B:
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case 0x3C:
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case 0x3D:
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case 0x3E:
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case 0x3F:
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recMAD(shaderUnit, instruction);
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break;
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// case ShaderOpcodes::RCP: recRCP(shaderUnit, instruction); break;
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// case ShaderOpcodes::RSQ: recRSQ(shaderUnit, instruction); break;
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// Unimplemented opcodes that don't seem to actually be used but exist in the binary
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// EMIT/SETEMIT are used in geometry shaders, however are sometimes found in vertex shaders?
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// case ShaderOpcodes::EMIT:
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// case ShaderOpcodes::SETEMIT:
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// log("[ShaderJIT] Unknown PICA opcode: %02X\n", opcode);
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// emitPrintLog(shaderUnit);
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// break;
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// case ShaderOpcodes::BREAK:
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// case ShaderOpcodes::BREAKC: Helpers::warn("[Shader JIT] Unimplemented BREAK(C) instruction!"); break;
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// We consider both MAD and MADI to be the same instruction and decode which one we actually have in recMAD
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// case 0x30:
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// case 0x31:
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// case 0x32:
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// case 0x33:
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// case 0x34:
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// case 0x35:
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// case 0x36:
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// case 0x37:
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// case 0x38:
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// case 0x39:
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// case 0x3A:
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// case 0x3B:
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// case 0x3C:
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// case 0x3D:
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// case 0x3E:
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// case 0x3F: recMAD(shaderUnit, instruction); break;
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// case ShaderOpcodes::SLT:
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// case ShaderOpcodes::SLTI: recSLT(shaderUnit, instruction); break;
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@ -221,9 +254,165 @@ void ShaderEmitter::storeRegister(QReg source, const PICAShader& shader, u32 des
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if (writeMask == 0xf) { // No lanes are masked, just use STR
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STR(source, statePointer, offset);
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} else {
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LDR(scratch1, statePointer, offset); // Load current source
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Helpers::panic("Unimplemented: Storing to register with blending");
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}
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LDR(scratch1, statePointer, offset); // Load current value
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LDR(scratch2, blendMasks.ptr<u8*>() + writeMask * 16); // Load write mask for blending
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BSL(scratch2.B16(), source.B16(), scratch1.B16()); // Scratch2 = (Source & mask) | (original & ~mask)
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STR(scratch2, statePointer, offset); // Write it back
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}
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}
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void ShaderEmitter::recDP3(const PICAShader& shader, u32 instruction) {
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const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];
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const u32 src1 = getBits<12, 7>(instruction);
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const u32 src2 = getBits<7, 5>(instruction);
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const u32 idx = getBits<19, 2>(instruction);
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const u32 dest = getBits<21, 5>(instruction);
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const u32 writeMask = getBits<0, 4>(operandDescriptor);
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// TODO: Safe multiplication equivalent (Multiplication is not IEEE compliant on the PICA)
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loadRegister<1>(src1_vec, shader, src1, idx, operandDescriptor);
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loadRegister<2>(src2_vec, shader, src2, 0, operandDescriptor);
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// Set W component of src1 to 0.0, so that the w factor of the following dp4 will become 0, making it equivalent to a dp3
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INS(src1_vec.Selem()[3], WZR);
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// Now do a full DP4
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FMUL(src1_vec.S4(), src1_vec.S4(), src2_vec.S4()); // Do a piecewise multiplication of the vectors first
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FADDP(src1_vec.S4(), src1_vec.S4(), src1_vec.S4()); // Now add the adjacent components together
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FADDP(src1_vec.toS(), src1_vec.toD().S2()); // Again for the bottom 2 lanes. Now the bottom lane contains the dot product
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if (writeMask != 0x8) { // Copy bottom lane to all lanes if we're not simply writing back x
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DUP(src1_vec.S4(), src1_vec.Selem()[0]); // src1_vec = src1_vec.xxxx
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}
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storeRegister(src1_vec, shader, dest, operandDescriptor);
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}
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void ShaderEmitter::recDP4(const PICAShader& shader, u32 instruction) {
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const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];
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const u32 src1 = getBits<12, 7>(instruction);
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const u32 src2 = getBits<7, 5>(instruction);
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const u32 idx = getBits<19, 2>(instruction);
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const u32 dest = getBits<21, 5>(instruction);
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const u32 writeMask = getBits<0, 4>(operandDescriptor);
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// TODO: Safe multiplication equivalent (Multiplication is not IEEE compliant on the PICA)
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loadRegister<1>(src1_vec, shader, src1, idx, operandDescriptor);
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loadRegister<2>(src2_vec, shader, src2, 0, operandDescriptor);
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FMUL(src1_vec.S4(), src1_vec.S4(), src2_vec.S4()); // Do a piecewise multiplication of the vectors first
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FADDP(src1_vec.S4(), src1_vec.S4(), src1_vec.S4()); // Now add the adjacent components together
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FADDP(src1_vec.toS(), src1_vec.toD().S2()); // Again for the bottom 2 lanes. Now the bottom lane contains the dot product
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if (writeMask != 0x8) { // Copy bottom lane to all lanes if we're not simply writing back x
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DUP(src1_vec.S4(), src1_vec.Selem()[0]); // src1_vec = src1_vec.xxxx
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}
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storeRegister(src1_vec, shader, dest, operandDescriptor);
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}
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void ShaderEmitter::recADD(const PICAShader& shader, u32 instruction) {
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const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];
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const u32 src1 = getBits<12, 7>(instruction);
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const u32 src2 = getBits<7, 5>(instruction);
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const u32 idx = getBits<19, 2>(instruction);
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const u32 dest = getBits<21, 5>(instruction);
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loadRegister<1>(src1_vec, shader, src1, idx, operandDescriptor);
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loadRegister<2>(src2_vec, shader, src2, 0, operandDescriptor);
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FADD(src1_vec.S4(), src1_vec.S4(), src2_vec.S4());
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storeRegister(src1_vec, shader, dest, operandDescriptor);
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}
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void ShaderEmitter::recMAX(const PICAShader& shader, u32 instruction) {
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const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];
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const u32 src1 = getBits<12, 7>(instruction);
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const u32 src2 = getBits<7, 5>(instruction);
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const u32 idx = getBits<19, 2>(instruction);
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const u32 dest = getBits<21, 5>(instruction);
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loadRegister<1>(src1_vec, shader, src1, idx, operandDescriptor);
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loadRegister<2>(src2_vec, shader, src2, 0, operandDescriptor);
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FMAX(src1_vec.S4(), src1_vec.S4(), src2_vec.S4());
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storeRegister(src1_vec, shader, dest, operandDescriptor);
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}
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void ShaderEmitter::recMIN(const PICAShader& shader, u32 instruction) {
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const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];
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const u32 src1 = getBits<12, 7>(instruction);
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const u32 src2 = getBits<7, 5>(instruction);
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const u32 idx = getBits<19, 2>(instruction);
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const u32 dest = getBits<21, 5>(instruction);
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loadRegister<1>(src1_vec, shader, src1, idx, operandDescriptor);
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loadRegister<2>(src2_vec, shader, src2, 0, operandDescriptor);
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FMIN(src1_vec.S4(), src1_vec.S4(), src2_vec.S4());
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storeRegister(src1_vec, shader, dest, operandDescriptor);
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}
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void ShaderEmitter::recMUL(const PICAShader& shader, u32 instruction) {
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const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];
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const u32 src1 = getBits<12, 7>(instruction);
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const u32 src2 = getBits<7, 5>(instruction); // src2 coming first because PICA moment
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const u32 idx = getBits<19, 2>(instruction);
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const u32 dest = getBits<21, 5>(instruction);
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// TODO: Safe multiplication equivalent (Multiplication is not IEEE compliant on the PICA)
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loadRegister<1>(src1_vec, shader, src1, idx, operandDescriptor);
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loadRegister<2>(src2_vec, shader, src2, 0, operandDescriptor);
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FMUL(src1_vec.S4(), src1_vec.S4(), src2_vec.S4());
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storeRegister(src1_vec, shader, dest, operandDescriptor);
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}
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void ShaderEmitter::recRSQ(const PICAShader& shader, u32 instruction) {
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const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];
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const u32 src = getBits<12, 7>(instruction);
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const u32 idx = getBits<19, 2>(instruction);
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const u32 dest = getBits<21, 5>(instruction);
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const u32 writeMask = operandDescriptor & 0xf;
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constexpr bool useAccurateRSQ = false;
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loadRegister<1>(src1_vec, shader, src, idx, operandDescriptor); // Load source 1 into scratch1
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// Compute reciprocal square root approximation
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// TODO: Should this use frsqte or fsqrt+div? The former is faster but less accurate
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// PICA RSQ uses f24 precision though, so it'll be inherently innacurate, and it's likely using an inaccurate approximation too, seeing as
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// It doesn't have regular sqrt/div instructions.
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// For now, we default to inaccurate inverse square root
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if constexpr (useAccurateRSQ) {
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FMOV(scratch1.S4(), FImm8(0x70)); // scratch1 = vec4(1.0f)
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FSQRT(src1_vec.toS(), src1_vec.toS()); // src1 = sqrt(src1), scalar
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FDIV(src1_vec.toS(), scratch1.toS(), src1_vec.toS()); // Now invert src1
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} else {
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FRSQRTE(src1_vec.toS(), src1_vec.toS()); // Much nicer
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}
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// If we only write back the x component to the result, we needn't perform a shuffle to do res = res.xxxx
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// Otherwise we do
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if (writeMask != 0x8) { // Copy bottom lane to all lanes if we're not simply writing back x
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DUP(src1_vec.S4(), src1_vec.Selem()[0]); // src1_vec = src1_vec.xxxx
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}
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storeRegister(src1_vec, shader, dest, operandDescriptor);
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}
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void ShaderEmitter::recMAD(const PICAShader& shader, u32 instruction) {
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const bool isMADI = getBit<29>(instruction) == 0;
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const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x1f];
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const u32 src1 = getBits<17, 5>(instruction);
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const u32 src2 = isMADI ? getBits<12, 5>(instruction) : getBits<10, 7>(instruction);
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const u32 src3 = isMADI ? getBits<5, 7>(instruction) : getBits<5, 5>(instruction);
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const u32 idx = getBits<22, 2>(instruction);
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const u32 dest = getBits<24, 5>(instruction);
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loadRegister<1>(src1_vec, shader, src1, 0, operandDescriptor);
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loadRegister<2>(src2_vec, shader, src2, isMADI ? 0 : idx, operandDescriptor);
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loadRegister<3>(src3_vec, shader, src3, isMADI ? idx : 0, operandDescriptor);
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// TODO: Safe PICA multiplication
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FMLA(src3_vec.S4(), src1_vec.S4(), src2_vec.S4());
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storeRegister(src3_vec, shader, dest, operandDescriptor);
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}
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void ShaderEmitter::recMOV(const PICAShader& shader, u32 instruction) {
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@ -236,4 +425,6 @@ void ShaderEmitter::recMOV(const PICAShader& shader, u32 instruction) {
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storeRegister(src1_vec, shader, dest, operandDescriptor);
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}
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void ShaderEmitter::recEND(const PICAShader& shader, u32 instruction) { RET(); }
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#endif
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