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wheremyfoodat 2022-12-31 15:54:24 +02:00
parent f2ab7a0370
commit 23a6ef447f
3 changed files with 11 additions and 5 deletions
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3
include/arm_defs.hpp
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@ -61,6 +61,7 @@ namespace FPSCR {
RoundToZero = 3 << 22,
// Default FPSCR value for threads
ThreadDefault = DefaultNan | FlushToZero | RoundToZero | IXC
ThreadDefault = DefaultNan | FlushToZero | RoundToZero,
MainThreadDefault = ThreadDefault | IXC;
};
}

4
src/core/CPU/cpu_dynarmic.cpp
View file

@ -9,7 +9,7 @@ CPU::CPU(Memory& mem, Kernel& kernel) : mem(mem), env(mem, kernel, *this) {
config.arch_version = Dynarmic::A32::ArchVersion::v6K;
config.callbacks = &env;
config.coprocessors[15] = cp15;
// config.define_unpredictable_behaviour = true;
config.define_unpredictable_behaviour = true;
config.global_monitor = &exclusiveMonitor;
config.processor_id = 0;
@ -18,7 +18,7 @@ CPU::CPU(Memory& mem, Kernel& kernel) : mem(mem), env(mem, kernel, *this) {
void CPU::reset() {
setCPSR(CPSR::UserMode);
setFPSCR(FPSCR::ThreadDefault);
setFPSCR(FPSCR::MainThreadDefault);
env.totalTicks = 0;
cp15->reset();

9
src/core/PICA/regs.cpp
View file

@ -4,8 +4,13 @@
using namespace Floats;
u32 GPU::readReg(u32 address) {
log("Ignoring read from GPU register %08X\n", address);
return 0;
if (address >= 0x1EF01000 && address < 0x1EF01C00) { // Internal registers
const u32 index = (address - 0x1EF01000) / sizeof(u32);
return readInternalReg(index);
} else {
log("Ignoring read to external GPU register %08X.\n", address);
return 0;
}
}
void GPU::writeReg(u32 address, u32 value) {