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Moar arm64 shader ops
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wheremyfoodat
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commit
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1 changed files with 157 additions and 20 deletions
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@ -128,8 +128,8 @@ void ShaderEmitter::compileInstruction(const PICAShader& shaderUnit) {
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switch (opcode) {
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case ShaderOpcodes::ADD: recADD(shaderUnit, instruction); break;
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case ShaderOpcodes::CALL: recCALL(shaderUnit, instruction); break;
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// case ShaderOpcodes::CALLC: recCALLC(shaderUnit, instruction); break;
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// case ShaderOpcodes::CALLU: recCALLU(shaderUnit, instruction); break;
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case ShaderOpcodes::CALLC: recCALLC(shaderUnit, instruction); break;
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case ShaderOpcodes::CALLU: recCALLU(shaderUnit, instruction); break;
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case ShaderOpcodes::CMP1:
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case ShaderOpcodes::CMP2: recCMP(shaderUnit, instruction); break;
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case ShaderOpcodes::DP3: recDP3(shaderUnit, instruction); break;
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@ -138,13 +138,13 @@ void ShaderEmitter::compileInstruction(const PICAShader& shaderUnit) {
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// case ShaderOpcodes::DPHI: recDPH(shaderUnit, instruction); break;
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case ShaderOpcodes::END: recEND(shaderUnit, instruction); break;
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// case ShaderOpcodes::EX2: recEX2(shaderUnit, instruction); break;
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// case ShaderOpcodes::FLR: recFLR(shaderUnit, instruction); break;
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case ShaderOpcodes::FLR: recFLR(shaderUnit, instruction); break;
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case ShaderOpcodes::IFC: recIFC(shaderUnit, instruction); break;
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case ShaderOpcodes::IFU: recIFU(shaderUnit, instruction); break;
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case ShaderOpcodes::JMPC: recJMPC(shaderUnit, instruction); break;
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// case ShaderOpcodes::JMPU: recJMPU(shaderUnit, instruction); break;
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case ShaderOpcodes::JMPU: recJMPU(shaderUnit, instruction); break;
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// case ShaderOpcodes::LG2: recLG2(shaderUnit, instruction); break;
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// case ShaderOpcodes::LOOP: recLOOP(shaderUnit, instruction); break;
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case ShaderOpcodes::LOOP: recLOOP(shaderUnit, instruction); break;
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case ShaderOpcodes::MOV: recMOV(shaderUnit, instruction); break;
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case ShaderOpcodes::MOVA: recMOVA(shaderUnit, instruction); break;
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case ShaderOpcodes::MAX: recMAX(shaderUnit, instruction); break;
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@ -156,14 +156,11 @@ void ShaderEmitter::compileInstruction(const PICAShader& shaderUnit) {
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// Unimplemented opcodes that don't seem to actually be used but exist in the binary
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// EMIT/SETEMIT are used in geometry shaders, however are sometimes found in vertex shaders?
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// case ShaderOpcodes::EMIT:
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// case ShaderOpcodes::SETEMIT:
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// log("[ShaderJIT] Unknown PICA opcode: %02X\n", opcode);
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// emitPrintLog(shaderUnit);
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// break;
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case ShaderOpcodes::EMIT:
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case ShaderOpcodes::SETEMIT: log("[ShaderJIT] Unimplemented PICA opcode: %02X\n", opcode); break;
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// case ShaderOpcodes::BREAK:
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// case ShaderOpcodes::BREAKC: Helpers::warn("[Shader JIT] Unimplemented BREAK(C) instruction!"); break;
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case ShaderOpcodes::BREAK:
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case ShaderOpcodes::BREAKC: Helpers::warn("[Shader JIT] Unimplemented BREAK(C) instruction!"); break;
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// We consider both MAD and MADI to be the same instruction and decode which one we actually have in recMAD
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case 0x30:
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@ -181,15 +178,13 @@ void ShaderEmitter::compileInstruction(const PICAShader& shaderUnit) {
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case 0x3C:
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case 0x3D:
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case 0x3E:
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case 0x3F:
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recMAD(shaderUnit, instruction);
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break;
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case 0x3F: recMAD(shaderUnit, instruction); break;
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// case ShaderOpcodes::SLT:
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// case ShaderOpcodes::SLTI: recSLT(shaderUnit, instruction); break;
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case ShaderOpcodes::SLT:
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case ShaderOpcodes::SLTI: recSLT(shaderUnit, instruction); break;
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// case ShaderOpcodes::SGE:
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// case ShaderOpcodes::SGEI: recSGE(shaderUnit, instruction); break;
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case ShaderOpcodes::SGE:
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case ShaderOpcodes::SGEI: recSGE(shaderUnit, instruction); break;
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default: Helpers::panic("Shader JIT: Unimplemented PICA opcode %X", opcode);
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}
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@ -430,6 +425,17 @@ void ShaderEmitter::recMOV(const PICAShader& shader, u32 instruction) {
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storeRegister(src1_vec, shader, dest, operandDescriptor);
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}
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void ShaderEmitter::recFLR(const PICAShader& shader, u32 instruction) {
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const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];
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const u32 src = getBits<12, 7>(instruction);
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const u32 idx = getBits<19, 2>(instruction);
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const u32 dest = getBits<21, 5>(instruction);
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loadRegister<1>(src1_vec, shader, src, idx, operandDescriptor); // Load source 1 into scratch1
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FRINTM(src1_vec.S4(), src1_vec.S4()); // Floor it and store into dest
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storeRegister(src1_vec, shader, dest, operandDescriptor);
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}
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void ShaderEmitter::recMOVA(const PICAShader& shader, u32 instruction) {
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const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];
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const u32 src = getBits<12, 7>(instruction);
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@ -630,6 +636,42 @@ void ShaderEmitter::recMAD(const PICAShader& shader, u32 instruction) {
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storeRegister(src3_vec, shader, dest, operandDescriptor);
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}
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void ShaderEmitter::recSLT(const PICAShader& shader, u32 instruction) {
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const bool isSLTI = (instruction >> 26) == ShaderOpcodes::SLTI;
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const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];
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const u32 src1 = isSLTI ? getBits<14, 5>(instruction) : getBits<12, 7>(instruction);
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const u32 src2 = isSLTI ? getBits<7, 7>(instruction) : getBits<7, 5>(instruction);
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const u32 idx = getBits<19, 2>(instruction);
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const u32 dest = getBits<21, 5>(instruction);
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loadRegister<1>(src1_vec, shader, src1, isSLTI ? 0 : idx, operandDescriptor);
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loadRegister<2>(src2_vec, shader, src2, isSLTI ? idx : 0, operandDescriptor);
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// Set each lane of SRC1 to FFFFFFFF if src2 > src1, else to 0. NEON does not have FCMLT so we use FCMGT with inverted operands
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// This is more or less a direct port of the relevant x64 JIT code
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FCMGT(src1_vec.S4(), src2_vec.S4(), src1_vec.S4());
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AND(src1_vec.B16(), src1_vec.B16(), onesVector.B16()); // AND with vec4(1.0) to convert the FFFFFFFF lanes into 1.0
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storeRegister(src1_vec, shader, dest, operandDescriptor);
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}
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void ShaderEmitter::recSGE(const PICAShader& shader, u32 instruction) {
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const bool isSGEI = (instruction >> 26) == ShaderOpcodes::SGEI;
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const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];
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const u32 src1 = isSGEI ? getBits<14, 5>(instruction) : getBits<12, 7>(instruction);
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const u32 src2 = isSGEI ? getBits<7, 7>(instruction) : getBits<7, 5>(instruction);
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const u32 idx = getBits<19, 2>(instruction);
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const u32 dest = getBits<21, 5>(instruction);
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loadRegister<1>(src1_vec, shader, src1, isSGEI ? 0 : idx, operandDescriptor);
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loadRegister<2>(src2_vec, shader, src2, isSGEI ? idx : 0, operandDescriptor);
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// Set each lane of SRC1 to FFFFFFFF if src1 >= src2, else to 0.
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// This is more or less a direct port of the relevant x64 JIT code
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FCMGE(src1_vec.S4(), src1_vec.S4(), src2_vec.S4());
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AND(src1_vec.B16(), src1_vec.B16(), onesVector.B16()); // AND with vec4(1.0) to convert the FFFFFFFF lanes into 1.0
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storeRegister(src1_vec, shader, dest, operandDescriptor);
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}
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void ShaderEmitter::recCMP(const PICAShader& shader, u32 instruction) {
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const u32 operandDescriptor = shader.operandDescriptors[instruction & 0x7f];
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const u32 src1 = getBits<12, 7>(instruction);
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@ -742,6 +784,28 @@ void ShaderEmitter::recCALL(const PICAShader& shader, u32 instruction) {
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LDP(XZR, X30, SP, POST_INDEXED, 16);
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}
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void ShaderEmitter::recCALLC(const PICAShader& shader, u32 instruction) {
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Label skipCall;
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// z is 1 if the call should be taken, 0 otherwise
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checkCmpRegister(shader, instruction);
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B(NE, skipCall);
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recCALL(shader, instruction);
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l(skipCall);
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}
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void ShaderEmitter::recCALLU(const PICAShader& shader, u32 instruction) {
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Label skipCall;
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// z is 0 if the call should be taken, 1 otherwise
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checkBoolUniform(shader, instruction);
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B(EQ, skipCall);
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recCALL(shader, instruction);
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l(skipCall);
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}
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void ShaderEmitter::recIFC(const PICAShader& shader, u32 instruction) {
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// z is 1 if true, else 0
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checkCmpRegister(shader, instruction);
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@ -801,10 +865,83 @@ void ShaderEmitter::recJMPC(const PICAShader& shader, u32 instruction) {
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B(EQ, l);
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}
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void ShaderEmitter::recJMPU(const PICAShader& shader, u32 instruction) {
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bool jumpIfFalse = instruction & 1; // If the LSB is 0 we want to compare to true, otherwise compare to false
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const u32 dest = getBits<10, 12>(instruction);
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Label& l = instructionLabels[dest];
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// Z is 0 if the uniform is true
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checkBoolUniform(shader, instruction);
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if (jumpIfFalse) {
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B(EQ, l);
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} else {
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B(NE, l);
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}
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}
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void ShaderEmitter::recLOOP(const PICAShader& shader, u32 instruction) {
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const u32 dest = getBits<10, 12>(instruction);
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const u32 uniformIndex = getBits<22, 2>(instruction);
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if (loopLevel > 0) {
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log("[Shader JIT] Detected nested loop. Might be broken?\n");
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}
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if (dest < recompilerPC) {
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Helpers::panic("[Shader JIT] Detected backwards loop\n");
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}
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loopLevel++;
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// Offset of the uniform
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const auto& uniform = shader.intUniforms[uniformIndex];
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const uintptr_t uniformOffset = uintptr_t(&uniform[0]) - uintptr_t(&shader);
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// Offset of the loop register
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const uintptr_t loopRegOffset = uintptr_t(&shader.loopCounter) - uintptr_t(&shader);
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LDRB(W0, statePointer, uniformOffset); // W0 = loop iteration count
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LDRB(W1, statePointer, uniformOffset + sizeof(u8)); // W1 = initial loop counter value
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LDRB(W2, statePointer, uniformOffset + 2 * sizeof(u8)); // W2 = Loop increment
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ADD(W0, W0, 1); // The iteration count is actually uniform.x + 1
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STR(W1, statePointer, loopRegOffset); // Set loop counter
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// Push loop iteration counter & loop increment
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// TODO: This might break if an instruction in a loop decides to yield...
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STP(X0, X2, SP, PRE_INDEXED, -16);
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Label loopStart, loopEnd;
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l(loopStart);
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compileUntil(shader, dest + 1);
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const size_t stackOffsetOfLoopIncrement = 0;
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const size_t stackOffsetOfIterationCounter = stackOffsetOfLoopIncrement + 8;
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LDP(X0, X2, SP); // W0 = loop iteration, W2 = loop increment
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LDR(W1, statePointer, loopRegOffset); // W1 = loop register
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// Increment loop counter
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ADD(W1, W1, W2);
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STR(W1, statePointer, loopRegOffset);
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// Subtract 1 from loop iteration counter,
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SUBS(W0, W0, 1);
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B(EQ, loopEnd);
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// Loop hasn't ended: Write back new iteration counter and go back to the start
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STR(X0, SP);
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B(loopStart);
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l(loopEnd);
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// Remove the stuff we pushed on the stack earlier
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ADD(SP, SP, 16);
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loopLevel--;
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}
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void ShaderEmitter::recEND(const PICAShader& shader, u32 instruction) {
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// Fetch original LR and return. This also restores SP to its original value, discarding the return guard into XZR
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LDP(XZR, X30, SP, POST_INDEXED, 16);
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RET();
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}
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#endif
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#endif
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